AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 188
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 188 of 858
- Download datasheet (13Mb)
13.5.3.3
13.5.3.4
13.5.3.5
32099F–11/2010
Disabling the DFLL
Open loop operation
Closed-loop operation
Before reading the value in any of the DFLL configuration registers a one must be written to the
Synchronization bit (SYNC) in the DFLLn Synchronization Register (DFLLnSYNC). The DFLL
configuration registers are ready to be read when PCLKSR.DFLLnRDY is set.
The DFLL is disabled by writing a zero to DFLLnCONF.EN. No other bits or fields in DFLLn-
CONF must be changed simultaneously.
After disabling the DFLL, PCLKSR.DFLLnRDY will not be set. It is not required to wait for
PCLKSR.DFLLnRDY to be set before re-enabling the DFLL.
After enabling the DFLL, open loop mode is selected by writing a zero to the Mode Selection bit
(MODE) in DFLLnCONF. When operating in open loop mode the output frequency of the DFLL
will be determined by the values written to the Coarse Calibration Value field (COARSE) and the
Fine Calibration Value field (FINE) in the DFLLnCONF register. When writing to COARSE and
FINE, be aware that the output frequency must not exceed the maximum frequency of the
device after the division in the clock generator. It is possible to change the value of COARSE
and FINE, and thereby the output frequency of the DFLL, while the DFLL is enabled and in use.
The DFLL clock is ready to be used when PCLKSR.DFLLnRDY is cleared after enabling the
DFLL.
The DFLL must be correctly configured before closed-loop operation can be enabled. After
e n a b l i n g t h e D F L L , e n a b l e a n d s e l e c t a r e f e r e n c e c l o c k ( C L K _ D F L L I F _ R E F ) .
CLK_DFLLIF_REF is a generic clock, please refer to Generic Clocks section for details. Then
set the maximum step size allowed in finding the COARSE and FINE values by setting the
Coarse Maximum Step field (CSTEP) and Fine Maximum Step field (FSTEP) in the DFLLn Max-
imum Step Register (DFLLnSTEP). A small step size will ensure low overshoot on the output
frequency, but can typically result in longer lock times. A high value might give a big overshoot,
but can typically give faster locking. DFLLnSTEP.CSTEP and DFLLnSTEP.FSTEP should not
be lower than 50% of the maximum value of DFLLnCONF.COARSE and DFLLnCONF.FINE
respectively. Then select the multiplication factor in the Integer Multiply Factor field (IMUL) and
the Fractional Multiply field (FMUL) in the DFLLn Multiplier Register (DFLLnMUL). Care must be
taken when choosing IMUL and FMUL so the output frequency does not exceed the maximum
frequency of the device. Start the closed-loop mode by writing a one to DFLLnCONF.MODE bit.
The frequency of CLK_DFLL (f
where f
only in closed-loop mode, and are controlled by the DFLLIF to meet user specified frequency.
The values in COARSE when the closed-loop mode is enabled is used by the frequency tuner
as a starting point for COARSE. Setting COARSE to a value close to the final value will reduce
the time needed to get a lock on COARSE.
Frequency locking
The locking of the frequency in closed-loop mode is divided into three stages. In the COARSE
stage the control logic quickly finds the correct value for DFLLnCONF.COARSE and thereby
sets the output frequency to a value close to the correct frequency. The DFLLn Locked on
REF
is the frequency of CLK_DFLLIF_REF. COARSE and FINE in DFLLnCONF are read-
DFLL
f
) is given by:
DFLL
=
⎛
⎝
IMUL
+
FMUL
---------------- -
2
16
⎞ f
⎠
AT32UC3L016/32/64
REF
188
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