AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 292
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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Figure 16-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge
Figure 16-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge
16.6.3
16.6.4
32099F–11/2010
EXTINTn/NMI
EXTINTn/NMI
Non-Maskable Interrupt
Asynchronous Interrupts
FILTER off
FILTER on
FILTER off
FILTER on
ISR.INTn:
ISR.INTn:
ISR.INTn:
ISR.INTn:
CLK_SYNC
CLK_SYNC
The NMI supports the same features as the external interrupts, and is accessed through the
same registers. The description in
instead of the INTn bits.
The NMI is non-maskable within the CPU in the sense that it can interrupt any other execution
mode. Still, as for the other external interrupts, the actual NMI input can be enabled and disabled
by accessing the registers in the EIC.
Each external interrupt can be made asynchronous by writing a one to INTn in the ASYNC reg-
ister. This will route the interrupt signal through the asynchronous path of the module. All edge
interrupts will be interpreted as level interrupts and the filter is disabled. If an interrupt is config-
ured as edge triggered interrupt in asynchronous mode, a zero in EDGE.INTn will be interpreted
as low level, and a one in EDGE.INTn will be interpreted as high level.
EIC_WAKE will be set immediately after the source triggers the interrupt, while the correspond-
ing bit in ISR and the interrupt to the interrupt controller will be set on the next rising edge of
CLK_SYNC. Please refer to
Figure 16-4 on page 293
Section 16.6.1
should be followed, accessing the NMI bit
for details.
AT32UC3L016/32/64
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