M30833FJFP#U3 Renesas Electronics America, M30833FJFP#U3 Datasheet - Page 201

• Manufacturer Part Number: M30833FJFP#U3
• Description: IC M32C/83 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJFP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
Figure 16.4 U0C0 to U4C0 Registers
2
0
1
9
C
3 .
B
8 /
0
1
3
0
3
J
G
4
a
0 -
n
o r
UARTi Transmit/Receive Control Register 0
b7
3 .
1
u
NOTES:
, 1
3
p
b6
1
2
(
1. P7
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
3. The UFORM bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to "001
4. If the CLK1 and CLK0 bits are changed, set the UiBRG register.
M
0
b5
0
(clock synchronous serial I/O mode), or "101
SMD2 to SMD0 bits are set to "100
transfer data).
Set this bit to "1" when the SMD2 to SMD0 bits are set to "010
3
6
2
b4
0
C
/TxD2 are ports for the N-channel open drain output, but not for the CMOS output.
8 /
Page 176
b3
, 3
b2
M
b1
3
2
C
b0
f o
8 /
4
3
UFORM
TXEPT
8
Symbol
CKPOL
CLK0
CLK1
) T
CRS
CRD
NCH
8
Bit
Symbol
U0C0 to U4C0
Data Output Select
Bit
UiBRG Count
Source Select Bit
CST/RTS Function
Select Bit
Transmit Register
Empty Flag
CTS/RTS Disable
Bit
CLK Polarity
Select Bit
Transfer Format
Select Bit
(1)
2
"(UART mode, 7-bit transfer data) or "110
Bit Name
(3)
Address
036C
2
" (UART mode, 8-bit transfer data).
16,
(4)
02EC
b0
0 0: Selects f
0 1: Selects f
1 0: Selects f
1 1: Do not set to this value
Enabled when CRD=0
0 : Selects CTS function
1 : Selects RTS function
0 : Data in the transmit register
1 : No data in the transmit register
0 : Enables CTS/RTS function
1 : Disables CTS/RTS function
0 : TxDi/SDAi and SCLi are ports for the
1 : TxDi/SDAi and SCLi are ports for the
0 : Data is transmitted on the falling edge
1 : Data is transmitted on the rising edge of
0 : LSB first
1 : MSB first
b1
(during transmission)
(transmission is completed)
CMOS output
N-channel open drain output
of the transfer clock and data is
received on the rising edge
the transfer clock and data is received
on the falling edge
16,
033C
(i=0 to 4)
2
16,
" (I
1
8
2n (2)
032C
2
C mode), and to "0" when the
Function
16,
02FC
16
2
"(UART mode, 9-bit
After Reset
0000 1000
2
2
"
RW
RW
RW
RW
RW
RW
RW
RW
RO
16. Serial I/O