M30833FJFP#U3 Renesas Electronics America, M30833FJFP#U3 Datasheet - Page 140

• Manufacturer Part Number: M30833FJFP#U3
• Description: IC M32C/83 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJFP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Table 12.1 DMAC Specifications
2
0
Channels
Transfer Memory Space
Maximum Bytes Transferred
DMA Request Factors
Channel Priority
Transfer Unit
Destination Address
Transfer Mode Single Transfer Transfer is completed when the DCTi register (i = 0 to 3) is set to "0000
DMA Interrupt Request Generation Timing When the DCTi register changes "0001
DMA Startup
DMA Stop
Reload Timing to the DCTi
or DMAi Register
DMA Transfer Cycles
NOTES:
DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i=0 to 3) or by using an interrupt
request, generated by the functions determined by the DSEL 4 to DSEL0 bits in the DMiSL register, as a
DMA request. Unlike interrupt requests, the I flag and interrupt control register do not affect DMA. There-
fore, a DMA request can be acknowledged even if an interrupt is disabled and cannot be acknowledged. In
addition, the IR bit in the interrupt control register does not change when a DMA request is acknowledged.
1
C
9
3 .
B
8 /
1. The IR bit in the interrupt control register does not change when a DMA request is acknowledged.
0
1
3
0
3
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4
a
0 -
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3 .
1
u
Item
, 1
3
p
1
2
(
M
0
0
3
Repeat Transfer When the DCTi register is set to "0000
Repeat Transfer DMA stops when the MDi1 to MDi0 bits are set to "00
Single Transfer DMA stops when the MDi1 to MDi0 bits are set to "00
6
Single Transfer DMA starts when a DMA request is generated after the DCTi register is
Repeat Transfer DMA starts when a DMA request is generated after the DCTi register is
2
C
8 /
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4
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128K bytes (when a 16-bit data is transferred) or 64K bytes (when an 8-
When the DCTi register is set to "0000
8
4 channels (cycle-steal method)
• From a desired address in a 16M-byte space to a fixed address in a
• From a fixed address in a 16M-byte space to a desired address in a
bit data is transferred)
Falling edge or both edges of input signals to the INT0 to INT3 pins
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 to UART4 transmit and receive interrupt requests
A/D conversion interrupt request
Intelligent I/O interrupt request
CAN interrupt request
Software trigger
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has highest priority)
8 bits, 16 bits
specifying source and destination addresses simultaneously)
is reloaded into the DCTi register and the DMA transfer is continued
set to "0001
= 0 to 1) are set to "01
set to "0001
peat transfer)
or when the DCTi register is set to "0000
transfer or write
DCTi register is set to "0000
fer mode
Minimum 3 cycles between SFR and internal RAM
Forward/fixed (forward and fixed directions cannot be specified when
16M-byte space
16M-byte space
16
16
" or more and the MDi1 to MD0 bits in the DMDj register (j
" or more and the MDi1 to MDi0 bits are set to "11
2
" (single transfer)
16
" and the DRCi register set to "0000
Specification
16
16
16
", the value of the DRCi register
" from "0001
" to "0000
16
" (0 DMA transfer) by DMA
________
16
16
2
"
" (DMA disabled)
" in repeat trans-
2
" or when the
________
12. DMAC
2
" (re-
16
16
"
"