D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 95

IC SUPER H MPU ROMLESS 208LQFP

D6417709SF167BV

Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of D6417709SF167BV

Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Notes: 1. The table shows the minimum number of execution cycles. The actual number of
Instruction
STC.L SSR,@–Rn
STC.L SPC,@–Rn
STC.L R0_BANK,
STC.L R1_BANK,
STC.L R2_BANK,
STC.L R3_BANK,
STC.L R4_BANK,
STC.L R5_BANK,
STC.L R6_BANK,
STC.L R7_BANK,
STS
STS
STS
STS.L MACH,@–Rn
STS.L MACL,@–Rn
STS.L PR,@–Rn
TRAPA #imm
@–Rn
@–Rn
@–Rn
@–Rn
@–Rn
@–Rn
@–Rn
@–Rn
MACH,Rn
MACL,Rn
PR,Rn
2. With the addressing modes using displacement (disp) listed below, the assembler
• When there is contention between an instruction fetch and data access
• When the destination register in a load (memory-to-register) instruction is also used
@ (disp:4, Rn) ; Register-indirect with displacement
@ (disp:8, Rn) ; GBR-indirect with displacement
@ (disp:8, PC) ; PC-relative with displacement
instruction execution cycles will increase in cases such as the following:
descriptions in this manual show the value before scaling ( 1, 2, or 4) is performed.
This is done to clarify the operation of the chip. For the actual assembler descriptions,
refer to the individual assembler notation rules.
disp:8, disp:12 ; PC-relative
by the next instruction
Operation
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
MACH
MACL
PR
Rn–4
Rn–4
Rn–4
PC
imm
Rn
SPC, SR
TRA
Rn, SSR
Rn, SPC
Rn, R0_BANK
Rn, R1_BANK
Rn, R2_BANK
Rn, R3_BANK
Rn, R4_BANK
Rn, R5_BANK
Rn, R6_BANK
Rn, R7_BANK
Rn, MACH
Rn, MACL
Rn, PR
Rn
Rn
SSR,
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
Code
0100nnnn00110011
0100nnnn01000011
0100nnnn10000011
0100nnnn10010011
0100nnnn10100011
0100nnnn10110011
0100nnnn11000011
0100nnnn11010011
0100nnnn11100011
0100nnnn11110011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
11000011iiiiiiii
Rev. 5.00, 09/03, page 49 of 760
Privileged
Mode
Cycles T Bit
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
8

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