D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 235
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123112/d6417709sf167bv_sml.jpg)
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.4.2
Standby mode is canceled by an interrupt (NMI, IRQ, IRL, PINT, or on-chip peripheral module)
or a reset.
Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects
an NMI, IRL, IRQ, PINT *
clock will be supplied to the entire chip and standby mode canceled after the time set in the
WDT’s timer control/status register has elapsed. The STATUS1 and STATUS0 pins both go low.
Interrupt handling then begins and a code indicating the interrupt source is set in the INTEVT and
INTEVT2 registers. After the branch to the interrupt handling routine, clear the STBY bit in the
STBCR register. WTCNT stops automatically. If the STBY bit is not cleared, WTCNT continues
operation and a transition is made to standby mode *
the data from being destroyed due to a rise in voltage with an unstable power supply, etc.
Interrupts are accepted in standby mode even when the BL bit in the SR register is 1. If necessary,
save SPC and SSR to the stack before executing the SLEEP instruction. Immediately after an
interrupt is detected, the phase of the CKIO pin clock output may be unstable, until the processor
starts interrupt handling. (The canceling condition is that the IRL3–IRL0 level is higher than the
mask level in the I3–I0 bits in the SR register.)
Notes: 1. When the RTC is being used, standby mode can be canceled using IRL3–IRL0, IRQ4–
WTCNT value
H'FF
H'80
2. Standby mode can be canceled with an RTC or TMU (only when running on the RTC
3. This standby mode can be canceled only by a power-on reset.
Canceling Standby Mode
IRQ0, or PINT0/1.
clock) interrupt.
Figure 8.1 Canceling Standby Mode with STBCR.STBY
Interrupt
request
1
, or on-chip peripheral module (except interval timer) *
Crystal oscillator settling
time and PLL synchronization
time
3
when it reaches H'80. This function prevents
WDT overflow and branch to
interrupt handling routine
Clear bit STBCR.STBY before
WTCNT reaches H'80. When
STBCR.STBY is cleared, WTCNT
halts automatically.
Rev. 5.00, 09/03, page 189 of 760
2
interrupt, the
Time
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