D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 583
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123112/d6417709sf167bv_sml.jpg)
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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16.3
16.3.1
For serial communication, the SCIF has an asynchronous mode in which characters are
synchronized individually. Refer to section 14.3.2, Operation in Asynchronous Mode. The SCIF
has a 16-byte FIFO buffer for both transmit and receive operations, reducing the overhead of the
CPU, and enabling continuous high-speed communication. Moreover, it has RTS and CTS signals
as modem control signals. The transmission format is selected in the serial mode register
(SCSMR), as shown in table 16.7. The SCIF clock source is selected by the combination of the
CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in table 16.8.
Table 16.7 SCSMR Settings and SCIF Communication Formats
Mode
Asynchronous
Data length is selectable: 7 or 8 bits.
Parity and multiprocessor bits are selectable, as is the stop bit length (1 or 2 bits). The
combination of the preceding selections constitutes the communication format and character
length.
In receiving, it is possible to detect framing errors (FER), parity errors (PER), receive FIFO
data full, receive data ready, and breaks.
In transmitting, it is possible to detect transmit FIFO data empty.
The number of stored data bytes is indicated for both the transmit and receive FIFO registers.
An internal or external clock can be selected as the SCIF clock source.
When an internal clock is selected, the SCIF operates using the on-chip baud rate
generator, and can output a serial clock signal with a frequency 16 times the bit rate.
When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The on-chip baud rate generator is not used.)
Operation
Overview
Bit 6
CHR
0
1
Bit 5
PE
0
1
0
1
SCSMR Settings
Bit 3
STOP
0
1
0
1
0
1
0
1
Data
Length
8-bit
7-bit
Parity
Bit
Not set
Set
Not set
Set
SCIF Communication Format
Stop Bit Length
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
Rev. 5.00, 09/03, page 537 of 760
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