D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 572
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123112/d6417709sf167bv_sml.jpg)
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
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Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 1—Receive FIFO Data Full (RDF): Indicates that receive data has been transferred to the
receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become greater
than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO control
register (SCFCR).
Bit 1: RDF
0
1
Note: * Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be read
Bit 0—Receive Data Ready (DR): Indicates that the quantity of data in the receive FIFO data
register (SCFRDR) is less than the specified receive trigger number, and that the next data has not
yet been received after the elapse of 15 etu from the last stop bit.
Bit 0: DR
0
1
Note: * This is equivalent to 1.5 frames with the 8-bit, 1-stop-bit format. (etu: elementary time unit)
Rev. 5.00, 09/03, page 526 of 760
when RDF is 1 is the specified receive trigger number. If an attempt is made to read after
all the data in SCFRDR has been read, the data is undefined. The quantity of receive data
in SCFRDR is indicated by the lower 8 bits of SCFTDR.
Description
The quantity of transmit data written to SCFRDR is less than the specified
receive trigger number
[Clearing conditions]
(1) By a power-on reset or in standby mode
(2) When the quantity of receive data in SCFRDR is less than the specified
The quantity of receive data in SCFRDR is greater than the specified receive
trigger number
[Setting condition]
When a quantity of receive data greater than the specified receive trigger number
is stored in SCFRDR *
Description
Receiving is in progress, or no receive data remains in SCFRDR after receiving
ended normally
[Clearing conditions]
(1) When the chip undergoes a power-on reset or enters standby mode
(2) When software reads DR after it has been set to 1, then writes 0 to DR
Next receive data has not been received
[Setting condition]
When SCFRDR contains less data than the specified receive trigger number,
and the next data has not yet been received after the elapse of 15 etu from the
last stop bit *
receive trigger value and 1 is read from RDF, which is then cleared to 0
(Initial value)
(Initial value)
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