D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 233
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123112/d6417709sf167bv_sml.jpg)
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 233 of 809
- Download datasheet (5Mb)
8.3
8.3.1
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral
modules continue to run in sleep mode and the clock continues to be output to the CKIO and
CKIO2 pins. In sleep mode, the STATUS1 pin is set high and the STATUS0 pin low.
8.3.2
Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, on-chip peripheral module, PINT) or
reset. Interrupts are accepted in sleep mode even when the BL bit in the SR register is 1. If
necessary, save SPC and SSR to the stack before executing the SLEEP instruction.
Canceling with an Interrupt: When an NMI, IRQ, IRL or on-chip peripheral module interrupt
occurs, sleep mode is canceled and interrupt exception handling is executed. A code indicating the
interrupt source is set in the INTEVT and INTEVT2 registers.
Canceling with a Reset: Sleep mode is canceled by a power-on reset or a manual reset.
8.3.3
DMAC transfers should not be performed in the sleep mode under conditions other than when the
clock ratio of I (on-chip clock) to B (bus clock) is 1:1.
Sleep Mode
Transition to Sleep Mode
Canceling Sleep Mode
Precautions when Using the Sleep Mode
Rev. 5.00, 09/03, page 187 of 760
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