D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 146

• Manufacturer Part Number: D6417709SF167BV
• Description: IC SUPER H MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417709SF167BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5. On-Chip Peripheral Interrupts
6. UDI Interrupt
4.6
Rev. 5.00, 09/03, page 100 of 760
— Conditions: The interrupt mask bits in SR are lower than the on-chip module (TMU, RTC,
— Operations: The PC value after the instruction at which the interrupt is accepted is saved to
— Conditions: An UDI interrupt command is input (see section 22.4.4, UDI Interrupt),
— Operations: The PC value after the instruction that accepts the interrupt is saved to SPC.
Return from exception handling
Operation when exception or interrupt occurs while SR.BL
SCI, IrDA, SCIF, A/D, DMAC, WDT, REF) interrupt level and the BL bit in SR is 0. The
interrupt is accepted at an instruction boundary.
SPC. SR at the point the interrupt is accepted is saved to SSR. The code corresponding to
the interrupt source is set in INTEVT and INTEVT2. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to VBR + H'0600. See section 6, Interrupt Controller (INTC),
for more information.
SR.IMASK is lower than 15, and the BL bit in SR is 0. The interrupt is accepted at an
instruction boundary.
SR at the point the interrupt is accepted is saved to SSR. H'5E0 is set to INTEVT and
INTEVT2. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to VBR +
H'0600. See section 6, Interrupt Controller (INTC), for more information.
Check the BL bit in SR with software. When SPC and SSR have been saved to external
memory, set the BL bit in SR to 1 before restoring them.
Issue an RTE instruction, which sets SPC in PC and SSR in SR, and causes a branch to the
SPC address, and return from exception handling.
Interrupt: Acceptance is suppressed until the BL bit in SR is cleared to 0. If there is an
interrupt request and the reception conditions are satisfied, the interrupt is accepted after
the execution of the instruction that clears the BL bit in SR to 0. In sleep or standby mode,
however, the interrupt will be accepted even when the BL bit in SR is 1.
Exception: No user break point trap will occur even when the break conditions are met.
When one of the other exceptions occurs, a branch is made to the fixed address of the reset
(H'A0000000). In this case, the values of the EXPEVT, SPC, and SSR registers are
undefined. Differently from general reset processing, the RESETOUT pin is not asserted,
and reset status is output from the STATUS0 and STATUS1 pins.
Cautions
1