D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 16
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section
20.3 Bus Master
Interface
Figure 20.2 A/D Data
Register Access
Operation (Reading
H'AA40)
23.1 Absolute
Maximum Ratings
Table 23.1 Absolute
Maximum Ratings
23.2 DC
Characteristics
Table 23.2 DC
Characteristics
Rev. 5.0, 09/03, page xiv of xliv
Page
622
657
659,
662
Description
Figure amended
Upper byte read
Lower byte read
Caution added
2.Until voltage is applied to all power supplies, a low level is input
at the RESETP pin, and CKIO has operated for a maximum of 4
clock cycles, internal circuits remain unsettled, and so pin states
are also undefined. The system design must ensure that these
undefined states do not cause erroneous system operation.
Note that the RESETP pin cannot receive a low level signal while
a low level signal is being input to the CA pin.
Test conditions for in sleep mode amended
Item
Sleep
mode *
Note * added
* If the IRL and IRLS interrupts are used, the minimum is 1.9 V.
data H'AA
data H'40
receives
receives
CPU
CPU
1
Symbol Min
Icc
IccQ
—
—
interface
interface
Bus
Bus
Typ Max Unit
15
10
ADDRn H
ADDRn H
30
20
[H'AA]
[H'AA]
Module internal data bus
Module internal data bus
ADDRn L
ADDRn L
Test Conditions
*
other external bus
cycle other than the
refresh cycle.
Vcc = 1.9 V
VccQ = 3.3 V
B = 33MHz
TEMP
TEMP
[H'40]
[H'40]
[H'40]
[H'40]
1
: When there is no
n = A to D
n = A to D
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