MC68332GVEH25 Freescale Semiconductor, MC68332GVEH25 Datasheet - Page 140

• Manufacturer Part Number: MC68332GVEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GVEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 132-QFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6-18
The following expressions apply to SCK baud rate:
or
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled
and assumes its inactive state value.
The DSCK field in command RAM determines the delay period from chip-select asser-
tion until the leading edge of the serial clock. The DSCKL field in SPCR1 determines
the period of delay before the assertion of SCK. The following expression determines
the actual delay before SCK:
where DSCKL equals {1, 2, 3,..., 127}.
When DSCK equals zero, DSCKL is not used. Instead, the PCS valid-to-SCK transi-
tion is one-half the DSCK period.
There are two transfer length options. The user can choose a default value of eight
bits, or a programmed value of eight to sixteen bits, inclusive. The programmed value
must be written into the BITS field in SPCR0. The BITSE field in command RAM de-
termines whether the default value (BITSE = 0) or the BITS value (BITSE = 1) is used.
Table 6-3 shows BITS field encoding.
Freescale Semiconductor, Inc.
PCS to SCK Delay
For More Information On This Product,
SPBR
SCK Baud Rate
QUEUED SERIAL MODULE
Go to: www.freescale.com
=
----------------------------------------------------------------------------------
2 SCK Baud Rate Desired
=
System Clock
----------------------------------------------------------------- -
System Clock Frequency
=
System Clock
----------------------------------- -
2 SPBR
DSCKL
USER’S MANUAL
MC68332