MC68332GVEH25 Freescale Semiconductor, MC68332GVEH25 Datasheet - Page 127

• Manufacturer Part Number: MC68332GVEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GVEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 132-QFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MC68332
USER’S MANUAL
form full duplex three-wire or half duplex two-wire transfers. A variety of transfer rate,
clocking, and interrupt-driven communication options are available.
Serial transfer of any number of bits from eight to sixteen can be specified. Program-
mable transfer length simplifies interfacing to a number of devices that require different
data lengths.
An inter-transfer delay of 17 to 8192 system clocks can be specified (default is 17 sys-
tem clocks). Programmable delay simplifies the interface to a number of devices that
require different delays between transfers.
A dedicated 80-byte RAM is used to store received data, data to be transmitted, and
a queue of commands. The CPU can access these locations directly. Serial peripher-
als can be treated like memory-mapped parallel devices.
The command queue allows the QSPI to perform up to 16 serial transfers without CPU
intervention. Each queue entry contains all the information needed by the QSPI to in-
dependently complete one serial transfer.
A pointer identifies the queue location containing the command for the next serial
transfer. Normally, the pointer address is incremented after each serial transfer, but
the CPU can change the pointer value at any time. Multiple-task support can be pro-
vided by segmenting the queue.
The QSPI has four peripheral chip-select pins. Chip-select signals simplify interfacing
by reducing CPU intervention. If chip-select signals are externally decoded, 16 inde-
pendent select signals can be generated. Each chip-select pin can drive up to four in-
dependent peripherals, depending on loading.
Wraparound operating mode allows continuous execution of queued commands. In
wraparound mode, newly received data replaces previously received data in receive
RAM. Wraparound can simplify the interface with A/D converters by continuously up-
dating conversion values stored in the RAM.
Continuous transfer mode allows simultaneous transfer of an uninterrupted bit stream.
Any number of bits in a range from 8 to 256 can be transferred without CPU interven-
tion. Longer transfers are possible, but minimal CPU intervention is required to prevent
loss of data. A standard delay of 17 system clocks is inserted between each queue
entry transfer.
Freescale Semiconductor, Inc.
For More Information On This Product,
QUEUED SERIAL MODULE
Go to: www.freescale.com
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