MC68332GVEH25 Freescale Semiconductor, MC68332GVEH25 Datasheet - Page 129

• Manufacturer Part Number: MC68332GVEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GVEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 132-QFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3.1.1 Control Registers
6.3.1.2 Status Register
6.3.2 QSPI RAM
6.3.2.1 Receive RAM
MC68332
USER’S MANUAL
Control registers contain parameters for configuring the QSPI and enabling various
modes of operation. The CPU has read and write access to all control registers, but
the QSM has read-only access to all bits except the SPE bit in SPCR1. Control regis-
ters must be initialized before the QSPI is enabled to ensure defined operation.
SPCR1 must be written last because it contains the QSPI enable bit (SPE).
Writing a new value to any control register except SPCR2 while the QSPI is enabled
disrupts operation. SPCR2 is buffered. New SPCR2 values become effective after
completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execu-
tion to restart at the designated location. Reads of SPCR2 return the current value of
the register, not of the buffer.
Writing the same value into any control register except SPCR2 while the QSPI is en-
abled has no effect on QSPI operation.
The QSPI status register (SPSR) contains information concerning the current serial
transmission. Only the QSPI can set the bits in this register. The CPU reads the SPSR
to obtain QSPI status information and writes it to clear status flags.
The QSPI contains an 80-byte block of dual-access static RAM that can be accessed
by both the QSPI and the CPU. The RAM is divided into three segments: receive data
RAM, transmit data RAM, and command control data RAM. Receive data is informa-
tion received from a serial device external to the MCU. Transmit data is information
stored by the CPU for transmission to an external device. Command control data is
used to perform transfers. Refer to Figure 6-3, which shows RAM organization.
Data received by the QSPI is stored in this segment. The CPU reads this segment to
retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused bits
in a receive queue entry are set to zero by the QSPI upon completion of the individual
queue entry. The CPU can access the data using byte, word, or long-word addressing.
The CPTQP value in SPSR shows which queue entries have been executed. The CPU
uses this information to determine which locations in receive RAM contain valid data
before reading them.
Freescale Semiconductor, Inc.
For More Information On This Product,
QUEUED SERIAL MODULE
Go to: www.freescale.com
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