MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 77

IC MCU 32BIT E300 324TEPBGA

MPC5125YVN400

Manufacturer Part Number
MPC5125YVN400
Description
IC MCU 32BIT E300 324TEPBGA
Manufacturer
Freescale Semiconductor
Series
MPC51xxr

Specifications of MPC5125YVN400

Core Processor
e300
Core Size
32-Bit
Speed
400MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, USB OTG
Peripherals
DMA, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
324-PBGA
Processor Series
MPC51xx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
1.4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
3.3 V
Interface Type
CAN, I2C
Minimum Operating Temperature
- 40 C
Program Memory Size
32 bit
Cpu Speed
400MHz
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Digital Ic Case Style
TEPBGA
No. Of Pins
324
Rohs Compliant
Yes
Cpu Family
MPC5xx
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
32KB
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC5125YVN400
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MPC5125YVN400
Manufacturer:
LTC
Quantity:
29
Part Number:
MPC5125YVN400
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
NOTES:
1
Freescale Semiconductor
Output timing is specified at a nominal 50 pF load.
Sym
10
1
2
3
4
5
6
7
8
9
(CLKPOL=0)
(CLKPOL=1)
SCK cycle time, programable in the PSC CCS register
SCK pulse width, 50% SCK duty cycle
Slave select clock delay, programmable in the PSC CCS register
Output data valid
Input data setup time
Input data hold time
Slave disable lag time
Sequential transfer delay, programable in the PSC CTUR / CTLR register
Clock falling time
Clock rising time
Output
MOSI
MISO
Input
Input
Input
SCK
Input
SCK
SS
Table 44. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)
Figure 42. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)
6
3
4
MPC5125 Microcontroller Data Sheet, Rev. 3
2
Description
1
7
2
5
Electrical and Thermal Characteristics
30.0
15.0
30.0
15.0
Min
6.0
1.0
8
TSCK
9
Max
8.9
7.9
7.9
1
Units SpecID
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A20.46
A20.47
A20.48
A20.49
A20.50
A20.51
A20.52
A20.53
A20.54
A20.55
77

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