MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 45

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2.3
NOTES:
1
2
3
4
4.2.4
The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled
core PLL.
NOTES:
1
2
3
Freescale Semiconductor
Sys PLL input clock frequency
Sys PLL input clock jitter
Sys PLL VCO frequency
Sys PLL VCO output jitter (Dj), peak to peak / cycle
Sys PLL VCO output jitter (Rj), RMS 1 sigma
Sys PLL relock time — after power up
Sys PLL relock time — when power was on
e300 frequency
e300 PLL VCO frequency
e300 PLL input clock frequency
e300 PLL input clock cycle time
e300 PLL relock time
The SYS_XTAL frequency and PLL configuration bits must be chosen such that the resulting system frequency, CPU (core)
frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies.
This represents total input jitter — short term and long term combined. Two different types of jitter can exist on the input to
CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter is passed into and through the
PLL to the internal clock circuitry.
PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached
during the power-on reset sequence.
PLL-relock time is the maximum amount of time required for the PLL lock after the PLL has been disabled and subsequently
re-enabled during sleep modes.
The frequency and e300 PLL configuration bits must be chosen such that the resulting system frequencies, CPU (core)
frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies in
Table
PLL-relock time is the maximum amount of time required for the PLL lock after a stable V
during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently
re-enabled during sleep modes.
The following hard-coded relationship exists between f
17.
System PLL Electrical Characteristics
e300 Core PLL Electrical Characteristics
1, 2
Characteristic
Characteristic
3
1
2
1
1
3
MPC5125 Microcontroller Data Sheet, Rev. 3
Table 15. System PLL Specifications
Table 16. e300 PLL Specifications
4
f
t
f
CSB_CLK
CSB_CLK
VCOcore
Sym
f
f
f
t
core
VCOjitterDj
VCOjitterRj
lock
f
core
f
VCOsys
sys_xtal
Sym
t
t
t
lock1
lock2
jitter
and f
VCOcore
Min
200
400
50
—
5
Min
400
16
—
—
—
—
—
: (f
core
Typical
= f
Typical
—
—
—
—
—
VCOcore
33.3
—
—
—
—
—
—
Electrical and Thermal Characteristics
DD
).
and CORE_SYSCLK are reached
Max
400
800
200
200
20
Max
800
200
170
67
10
40
12
Unit
MHz
MHz
MHz
Unit
MHz
MHz
ns
µs
ps
ps
ps
µs
µs
SpecID
SpecID
O4.1
O4.3
O4.4
O4.5
O4.6
O3.1
O3.2
O3.3
O3.4
O3.5
O3.6
O3.7
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