MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 53

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NOTES:
1
2
3
4
5
4.3.5.4
NOTES:
1
2
3
Figure 9
Freescale Semiconductor
Clock cycle time, CL = x
CK HIGH pulse width
CK LOW pulse width
Address, control, and data output setup time relative
to MCK rising edge
Address, control, and data output hold time relative to
MCK rising edge
Input data set-up time, relative to MCK
Input data hold time, relative to MCK
Measured with clock pin loaded with differential 100 Ω termination resistor.
Measured with all outputs except the clock loaded with 50 Ω termination resistor to V
All transitions measured at mid-supply (V
In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low.
The window position is given for t
SDRAM device. For other values of t
Measured with clock pin loaded with 50 Ω termination resistor to mid-supply.
Measured with all outputs except the clock loaded with 50 Ω termination resistor to V
All transitions measured at mid-supply (V
shows the DDR SDRAM write timing.
SDR SDRAM AC Timing Specifications
DQ, DM(out)
To achieve better timing, balance the loading of DQS as MCK although DQS is not used in
SDR mode.
Parameter
MCK
DQS
At recommended operating conditions with V
DQSEN
Table 24. SDR SDRAM Timing Specifications
DQSEN
MPC5125 Microcontroller Data Sheet, Rev. 3
= 2.5 t
DD_IO_MEM
DD_IO_MEM
t
DS
, the window position is shifted accordingly.
Figure 9. DDR Write Timing
CK
t
CH
t
t
(RDLY = 2, HALF DQS DLY = 1, QUART DQS DLY = 0) with CL = 3 DDR2
DQSS
DH
t
t
Symbol
/2).
/2).
OH(base)
OS(base)
t
t
t
t
t
CK
CH
CL
IS
IH
NOTE
t
CK
t
t
CK
CK
/2 – 1000
/2 – 1000
7500
1000
1000
0.43
0.43
Min
t
CL
DD_IO_MEM
Electrical and Thermal Characteristics
DD_IO_MEM
DD_IO_MEM
of ±5%
Max
0.57
0.57
—
—
—
—
—
/2.
/2.
Unit Notes SpecID
t
t
ps
ps
ps
ps
ps
CK
CK
1,3
2,3
1,3
2,3
3
3
A5.15
A5.16
A5.1
A5.3
A5.4
A5.6
A5.7
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