MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet - Page 40

• Manufacturer Part Number: MC56F8147VPYE
• Description: IC DSP 16BIT 40MHZ 160-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8147VPYE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 160-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Data Ram Size: 4 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 x 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.2.3
The recommended method of connecting an external clock is given in
source is connected to XTAL and the EXTAL pin is grounded. When using an external clock source, set
the OCCS_COHL bit high as well.
3.3 Registers
When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the
register definitions without the internal Relaxation Oscillator, since the 56F8347/56F8147 do NOT
contain this oscillator.
Part 4 Memory Map
4.1 Introduction
The 56F8347 and 56F8147 devices are 16-bit motor-control chips based on the 56800E core. These parts
use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memories are used in both spaces.
This section provides memory maps for:
On-chip memory sizes for each device are summarized in
identified in the “Use Restrictions” column of
Note: Data Flash and Program RAM are NOT available on the 56F8147 device.
40
Program Flash
Data Flash
Program RAM
Data RAM
Program Boot Flash
•
•
On-Chip Memory
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
External Clock Source
Figure 3-4 Connecting an External Clock Register
External
56F8347
XTAL
Clock
128KB
8KB
4KB
8KB
8KB
Table 4-1 Chip Memory Configurations
EXTAL
V
56F8347 Technical Data, Rev.11
SS
56F8147
128KB
8KB
8KB
—
—
Table
Note: When using an external clocking source
with this configuration, the input “CLKMODE”
should be high and the COHL bit in the OSCTL
register should be set to 1.
4-1.
Erase/Program via Flash interface unit and word writes to
CDBW
Erase/Program via Flash interface unit and word writes to
CDBW. Data Flash can be read via either CDBR or XDB2,
but not by both simultaneously
None
None
Erase/Program via Flash Interface unit and word to CDBW
Table
4-1. Flash memories’ restrictions are
Use Restrictions
Figure
3-4. The external clock
Freescale Semiconductor
Preliminary