MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet - Page 141

• Manufacturer Part Number: MC56F8147VPYE
• Description: IC DSP 16BIT 40MHZ 160-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8147VPYE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 160-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Data Ram Size: 4 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 x 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Freescale Semiconductor
Preliminary
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and
2. Parameters listed are guaranteed by design.
3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 2
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
RESET Assertion to Address, Data and Control
Signals High Impedance
Minimum RESET Assertion Duration
RESET Deassertion to First External Address
Output
Edge-sensitive Interrupt Request Width
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
Delay from IRQA Assertion (exiting Wait) to
External Data Memory Access
Delay from IRQA Assertion to External Data
Memory Access (exiting Stop)
IRQA Width Assertion to Recover from Stop
State
Stop modes), T = 125ns.
This is not the minimum required so that the IRQA interrupt is accepted.
5
3
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Characteristic
4
56F8347 Technical Data, Rev.11
t
IDM - FAST
t
t
t
Symbol
IG - FAST
IRI -FAST
IF - FAST
t
t
t
t
t
RDA
RAZ
IRW
t
t
IDM
t
t
RA
IRI
IW
IG
IF
Typical
1.5T
1.5T
Min
16T
63T
18T
14T
18T
14T
22T
18T
22T
18T
—
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Typical
Max
64T
21
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Figure
1,2
10-5
10-5
10-5
10-6
10-7
10-7
10-8
10-9
10-9
21
T.
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