MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet - Page 118

• Manufacturer Part Number: MC56F8147VPYE
• Description: IC DSP 16BIT 40MHZ 160-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8147VPYE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 160-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Data Ram Size: 4 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 x 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.5.10.2
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and
system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and
system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The
SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL)
to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible
means to manage power consumption.
Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may be shut
down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and
master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused.
Clock enables provide the means to disable individual clocks. Some peripherals provide further controls
to disable unused subfunctions. Refer to
Peripheral User Manual for further details.
6.7 Power-Down Modes Overview
The 56F8347/56F8147 operate in one of three power-down modes, as shown in
118
Run
Wait
Stop
Base + $E
RESET
Write
Read
Mode
Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
Figure 6-15 I/O Short Address Location Low Register (SIM_ISAL)
15
1
Active
Core and memory
clocks disabled
System clocks continue to be generated in
the SIM, but most are gated prior to
reaching memory, core and peripherals.
Core Clocks
14
Table 6-3 Clock Operation in Power-Down Modes
1
13
1
12
1
Active
Active
Peripheral Clocks
56F8347 Technical Data, Rev.11
11
1
Part 3 On-Chip Clock Synthesis
10
1
9
1
8
1
ISAL[21:6]
Device is fully functional
Peripherals are active and can produce interrupts if
they have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
The only possible recoveries from Stop mode are:
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
4. External reset
5. Power-on reset
7
1
6
1
5
1
Description
4
1
(OCCS), and the 56F8300
Table 6-3
3
1
Freescale Semiconductor
2
1
.
1
1
Preliminary
0
1