MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet - Page 148

• Manufacturer Part Number: MC56F8147VPYE
• Description: IC DSP 16BIT 40MHZ 160-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8147VPYE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 160-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Data Ram Size: 4 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 x 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.13 Serial Communication Interface (SCI) Timing
148
1. Parameters listed are guaranteed by design.
2. f
3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
Baud Rate
RXD
TXD
SCI receive
SCI receive
40MHz for the 56F8147 device.
MAX
4
Characteristic
3
data pin
data pin
Pulse Width
Pulse Width
is the frequency of operation of the system clock, ZCLK, in MHz, which is 60MHz for the 56F8347 device, and
(Input)
(Input)
RXD
TXD
Phase B
2
(Input)
Phase A
(Input)
Figure 10-15 Quadrature Decoder Timing
Symbol
RXD
TXD
BR
PW
PW
Figure 10-16 RXD Pulse Width
Figure 10-17 TXD Pulse Width
P
IN
Table 10-21 SCI Timing
56F8347 Technical Data, Rev.11
P
P
IN
0.965/BR
0.965/BR
PH
Min
—
RXD
TXD
P
PH
PW
PW
P
PH
P
P
HL
PH
(f
1.04/BR
1.04/BR
P
MAX
HL
Max
1
/16)
P
HL
P
HL
Mbps
Unit
ns
ns
Freescale Semiconductor
See Figure
10-16
10-17
—
Preliminary