MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet - Page 107

• Manufacturer Part Number: MC56F8147VPYE
• Description: IC DSP 16BIT 40MHZ 160-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8147VPYE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 160-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Data Ram Size: 4 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 x 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.5.1.2
This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with
the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings
can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset.
In addition, this pin can be used as a general purpose input pin after reset.
6.5.1.3
6.5.1.4
This bit is always read as 0. Writing a 1 to this bit will cause the part to reset.
6.5.1.5
6.5.1.6
6.5.2
Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A
reset (other than POR) will only set bits in the register; bits are not cleared. Only software should only clear
this register.
Freescale Semiconductor
Preliminary
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Base + $1
RESET
0 = External address bits [19:16] are initially programmed as GPIO
1 = When booted with EXTBOOT = 1, A[19:16] are initially programmed as address. If EXTBOOT is 0,
they are initialized as GPIO.
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
00 - Stop mode will be entered when the 56800E core executes a STOP instruction
01 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be
reprogrammed in the future
10 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then only be
changed by resetting the device
11 - Same operation as 10
00 - Wait mode will be entered when the 56800E core executes a WAIT instruction
01 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be
reprogrammed in the future
10 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then only be
changed by resetting the device
11 - Same operation as 10
Read
Write
SIM Reset Status Register (SIM_RSTSTS)
EMI_MODE (EMI_MODE)—Bit 6
OnCE Enable (OnCE EBL)—Bit 5
Software Reset (SW RST)—Bit 4
Stop Disable (STOP_DISABLE)—Bits 3–2
Wait Disable (WAIT_DISABLE)—Bits 1–0
15
0
0
Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)
14
0
0
13
0
0
12
0
0
56F8347 Technical Data, Rev.11
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
SWR
5
COPR
4
EXTR
3
POR
Register Descriptions
2
1
0
0
0
0
0
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