R5F212A8SNFP#U0 Renesas Electronics America, R5F212A8SNFP#U0 Datasheet - Page 488

• Manufacturer Part Number: R5F212A8SNFP#U0
• Description: IC R8C/2A MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 17.9
Hardware LIN Clear the status flags
Timer RA Set to start a pulse width measurement
Timer RA Read the count status flag
Hardware LIN Set to start Synch Break detection
Hardware LIN Read the RXD0 input status flag
Hardware LIN Read the Synch Break detection flag
Nov 26, 2007
TCSTF flag in the TRACR register
TSTART bit in the TRACR register ← 1
Example of Header Field Reception Flowchart (2)
RXDSF flag in the LINCR register
SBDCT flag in the LINST register
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST
register ← 1
LSTART bit in the LINCR register ← 1
RXDSF = 1 ?
SBDCT = 1 ?
TCSTF = 1 ?
YES
YES
YES
Page 466 of 580
A
B
NO
NO
NO
Timer RA waits until the timer starts
counting.
Zero to one cycle of the timer RA count
source is required after timer RA starts
counting before the TCSTF flag is set to
1.
Hardware LIN waits until the RXD0
input for UART0 is masked.
Do not apply “L” level to the RXD pin
until the RXDSF flag reads 1 after
writing 1 to the LSTART bit. This is
because the signal applied during this
time is input directly to UART0.
Three to five cycles of the CPU clock
are required after the LSTART bit is set
to 1 before the RXDSF flag is set to 1.
After this, input to timer RA and UART0
is enabled.
Hardware LIN detects a Synch Break.
The interrupt of the timer RA may be
used.
When Synch Break is detected, timer
RA is reloaded with the initially set
count value.
Even if the duration of the input “L”
level is shorter than the set period,
timer RA is reloaded with the initially
set count value and waits until the
next “L” level is input.
Three to five cycles of the CPU clock
are required after Synch Break
detection before the SBDCT flag is
set to 1.
When the SBE bit in the LINCR
register is set to 0 (unmasked after
Synch Break is detected), timer RA
can be used in timer mode after the
SBDCT flag in the LINST register is
set to 1 and the RXDSF flag is set to
0.
17. Hardware LIN