R5F212A8SNFP#U0 Renesas Electronics America, R5F212A8SNFP#U0 Datasheet - Page 171

• Manufacturer Part Number: R5F212A8SNFP#U0
• Description: IC R8C/2A MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
13. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows
selection of count source protection mode enable or disable.
Table 13.1 lists information on the Watchdog Timer Specifications.
Refer to 5.6 Watchdog Timer Reset for details on the watchdog timer.
Figure 13.1 shows the Block Diagram of Watchdog Timer. Figure 13.2 shows the Registers WDTR, WDTS, and
WDC. Figure 13.3 shows the Registers CSPR and OFS.
Table 13.1
Count source
Count operation
Count start condition
Count stop condition
Reset condition of watchdog
timer
Operation at the time of underflow Watchdog timer interrupt or
Select functions
Nov 26, 2007
Watchdog Timer Specifications
Item
Page 149 of 580
CPU clock
Decrement
Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Stop mode, wait mode
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
watchdog timer reset
• Division ratio of prescaler
• Count source protection mode
• Starts or stops of the watchdog timer after a reset
Selected by the WDC7 bit in the WDC register
Whether count source protection mode is enabled or disabled after a
reset can be selected by the CSPROINI bit in the OFS register (flash
memory). If count source protection mode is disabled after a reset, it
can be enabled or disabled by the CSPRO bit in the CSPR register
(program).
Selected by the WDTON bit in the OFS register (flash memory).
Count Source Protection
Mode Disabled
Low-speed on-chip oscillator
clock
None
Watchdog timer reset
Count Source Protection
Mode Enabled
13. Watchdog Timer