R5F212A8SNFP#U0 Renesas Electronics America, R5F212A8SNFP#U0 Datasheet - Page 166

• Manufacturer Part Number: R5F212A8SNFP#U0
• Description: IC R8C/2A MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
12.5
Figure 12.21
Table 12.8
Timer RC
Timer RD
Clock synchronous serial
I/O with chip select
I
2
The timer RC interrupt, timer RD (channel 0) interrupt, timer RD (channel 1) interrupt, clock synchronous serial
I/O with chip select interrupt, and I
interrupt request is generated by the logical OR of several interrupt request factors and is reflected in the IR bit in
the corresponding interrupt control register. Therefore, each of these peripheral functions has its own interrupt
request source status register (status register) and interrupt request source enable register (enable register) to
control the generation of interrupt requests (change the IR bit in the interrupt control register). Table 12.8 lists the
Registers Associated with Timer RC Interrupt, Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select
Interrupt, and I
C bus interface
Peripheral Function
Timer RC Interrupt, Timer RD Interrupt, Clock Synchronous Serial I/O with
Chip Select Interrupts, and I
Multiple Interrupt Request Sources)
Nov 26, 2007
Name
Channel 0
Channel 1
Registers Associated with Timer RC Interrupt, Timer RD Interrupt, Clock
Synchronous Serial I/O with Chip Select Interrupt, and I
Block Diagram of Timer RD Interrupt
2
C bus Interface Interrupt and Figure 12.21 shows a Block Diagram of Timer RD Interrupt.
i = 0 or 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register
OVIE bit
UDF bit
OVF bit
Page 144 of 580
Channel i
TRCSR
TRDSR0
TRDSR1
SSSR
ICSR
Interrupt Request Source
IMIEC bit
IMIED bit
IMIEA bit
IMIEB bit
IMFA bit
IMFB bit
IMFC bit
IMFD bit
Status Register of
2
C bus interface interrupt each have multiple interrupt request sources. An
2
C bus Interface Interrupt (Interrupts with
Interrupt Request Source
TRCIER
TRDIER0
TRDIER1
SSER
ICIER
Enable Register of
Timer RD (channel i)
interrupt request
(IR bit in TRDiIC register)
2
C bus Interface Interrupt
TRCIC
TRD0IC
TRD1IC
SSUIC
IICIC
Interrupt Control
Register
12. Interrupts