R5F212A8SNFP#U0 Renesas Electronics America, R5F212A8SNFP#U0 Datasheet - Page 240

• Manufacturer Part Number: R5F212A8SNFP#U0
• Description: IC R8C/2A MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
14.3.5
Table 14.19
Count source
Count operation
Count period
Waveform output timing
Count start condition
Count stop condition
Interrupt request generation
timing
TRCIOA, TRCIOB, TRCIOC,
and TRCIOD pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
j = A, B, C, or D
This function detects when the contents of the TRC register (counter) and the TRCGRj register (j = A, B, C, or
D) match (compare match). When a match occurs a signal is output from the TRCIOj pin at a given level. The
output compare function, or other mode or function, can be selected for each individual pin.
Table 14.19 lists the Specifications of Output Compare Function, Figure 14.47 shows a Block Diagram of
Output Compare Function, Figures 14.48 to 14.50 show registers associated with the output compare function,
Table 14.20 lists the Functions of TRCGRj Register when Using Output Compare Function, and Figure 14.51
shows an Operating Example of Output Compare Function.
Nov 26, 2007
Timer Mode (Output Compare Function)
Item
Specifications of Output Compare Function
Page 218 of 580
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Increment
• The CCLR bit in the TRCCR1 register is set to 0 (free running
• The CCLR bit in the TRCCR1 register is set to 1 (TRC register set to
Compare match
1 (count starts) is written to the TSTART bit in the TRCMR register.
0 (count stops) is written to the TSTART bit in the TRCMR register.
The output compare output pin retains output level before count stops,
the TRC register retains a value before count stops.
• Compare match (contents of registers TRC and TRCGRj match)
• The TRC register overflows.
Programmable I/O port or output compare output (selectable individually
by pin)
Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• Output compare output pin selected
• Compare match output level select
• Initial output level select
• Timing for clearing the TRC register to 0000h
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff
• Can be used as an internal timer by disabling timer RC output
operation): 1/fk × 65,536
fk: Count source frequency
0000h at TRCGRA compare match):
1/fk × (n + 1)
n: TRCGRA register setting value
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
“L” output, “H” output, or toggle output
Sets output level for period from count start to compare match
Overflow or compare match with the TRCGRA register
of Pulse Output.)
Specification
14. Timers