R5F212A8SNFP#U0 Renesas Electronics America, R5F212A8SNFP#U0 Datasheet - Page 167

• Manufacturer Part Number: R5F212A8SNFP#U0
• Description: IC R8C/2A MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
As with other maskable interrupts, the timer RC interrupt, timer RD (channel 0) interrupt, timer RD (channel 1)
interrupt, clock synchronous serial I/O with chip select interrupt, and I
the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since each interrupt source is
generated by a combination of multiple interrupt request sources, the following differences from other maskable
interrupts apply:
Refer to chapters of the individual peripheral functions (14.3 Timer RC, 14.4 Timer RD, 16.2 Clock
Synchronous Serial I/O with Chip Select (SSU) and 16.3 I
register.
Refer to 12.1.6 Interrupt Control for the interrupt control register.
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When bits in the enable register corresponding to bits set to 1 in the status register are set to 1 (enable
interrupt), the IR bit in the interrupt control register is set to 1 (interrupt requested).
When either bits in the status register or bits in the enable register corresponding to bits in the status register, or
both, are set to 0, the IR bit is set to 0 (interrupt not requested). Basically, even though the interrupt is not
acknowledged after the IR bit is set to 1, the interrupt request will not be maintained. Also, the IR bit is not set
to 0 even if 0 is written to the IR bit.
Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.
Therefore, the IR bit is also not automatically set to 0 when the interrupt is acknowledged. Set each bit in the
status register to 0 in the interrupt routine. Refer to the status register figure for how to set individual bits in the
status register to 0.
When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is
set to 1, the IR bit remains 1.
When multiple bits in the enable register are set to 1, determine by the status register which request source
causes an interrupt.
Nov 26, 2007
Page 145 of 580
2
C bus Interface) for the status register and enable
2
C bus interface interrupt are controlled by
12. Interrupts