R5F212A8SNFP#U0 Renesas Electronics America, R5F212A8SNFP#U0 Datasheet - Page 391

• Manufacturer Part Number: R5F212A8SNFP#U0
• Description: IC R8C/2A MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
14.6.2
Table 14.56
Count sources
Count operations
PWM waveform
Count start condition
Count stop condition
Interrupt request
generation timing
TRFO00 to TRFO12 pins
function
Counter value reset timing
Read from timer
Write to timer
Select functions
In output compare mode, when the value of the TRF register matches the value of the TRFM0 (compare 0 match)
or TRFM1 (compare 1 match) register, a user-set level is output mode from the output-compare output pin.
Table 14.56 shows the Output Compare Mode Specifications. Table 14.57 shows the Output in Output
Compare Mode (Example of TRFO00 Pin). Figure 14.183 shows an Operating Example in Output Compare
Mode. Figure 14.184 shows the Operating Example in Output Compare Mode (“L” and “H” Held Output in
Count Stops).
Nov 26, 2007
Output Compare Mode
Item
Output Compare Mode Specifications
Page 369 of 580
f1, f8, f32
Increment
PWM period: 1/fk × (n + 1)
“L” level width: 1/fk × (m + 1)
“H” level width: 1/fk × (n - m)
The TSTART bit in the TRFCR0 register is set to 1 (count starts).
The TSTART bit in the TRFCR0 register is set to 0 (count stops).
• When compare 0 match is generated [compare 0 interrupt]
• When compare 1 match is generated [compare 1 interrupt]
• When time RF overflows [timer RF interrupt].
Programmable I/O port or output-compare output
In the following cases, the value in the TRF register is set to 0000h.
• When the TSTART bit in the TRFCR0 register is set to 0 (count stops).
• The CCLR bit in the TRFCR1 register is set to 1 (the TRF register is set to
• The count value can be read out by reading the TRF register.
• The value in the compare register can be read out by reading registers
Write to the TRF register is disabled
• Output-compare output pin selected
• Output level at the compare match
• Output level inverted
• Output level at the count stops
• Timing to set the TRF register to 0000h
fk: Frequency of count source
m: Value set in the TRFM0 register
n: Value set in the TRFM1 register
0000h at compare 1 match) in the compare 1 matches.
TRFM0 and TRFM1.
Either 1 pin or multiple pins among TRFO00 to TRFO02, or TRFO10 to
TRFO12 (bits TRFOUT0 to TRFOUT5 in the TRFOUT register).
Selects “H”, “L”, inverted, or unchanged (bits TRFC14 to TRFC17 in the
TRFCR1 register).
Selects output level inverted or not inverted (bits TRFOUT6 to TRFOUT7
in the TRFOUT register).
Selects “H”, “L”, or unchanged (bits TRFC05 to TRFC06 in the TRFCR0
register).
Overflow or compare 1 match in the TRFM1 register (the CCLR bit in the
TRFCR1 register).
m + 1
n + 1
n - m
Specification
It applies under the following conditions.
• CMP output “H” when compare 0 is matched
• CMP output “L” when compare 1 is matched
• CMP output not inverted
14. Timers