R5F212A8SNFP#U0 Renesas Electronics America, R5F212A8SNFP#U0 Datasheet - Page 304

• Manufacturer Part Number: R5F212A8SNFP#U0
• Description: IC R8C/2A MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Table 14.42
i = 0 or 1
Count sources
Count operations
PWM waveform
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOA1 pin function
TRDIOB0, TRDIOC0, TRDIOD0,
TRDIOB1, TRDIOC1, TRDIOD1
pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
Nov 26, 2007
PWM Mode Specifications
Item
Page 282 of 580
f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a
program)
Increment
PWM period: 1/fk x (m+1)
Active level width: 1/fk x (m-n)
Inactive level width: 1/fk x (n+1)
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
• 0 (count stops) is written to the TSTARTi bit in the TRDSTR register
• When the CSELi bit in the TRDSTR register is set to 0, the count
• Compare match (The content of the TRDi register matches content of
• TRDi register overflows
Programmable I/O port or TRDCLK (external clock) input
Programmable I/O port
Programmable I/O port or pulse output (selectable by pin)
Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
The count value can be read by reading the TRDi register.
The value can be written to the TRDi register.
• 1 to 3 PWM output pins selected per 1 channel
• The active level selected by pin.
• Initial output level selected by pin.
• Synchronous operation (Refer to 14.4.3 Synchronous Operation.)
• Buffer operation (Refer to 14.4.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse Output
fk: Frequency of count source
m: Value set in the TRDGRAi (i = 0 or 1) register
n: Value set in the TRDGRji (j = B, C, or D) register
when the CSELi bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops.
stops at the compare match in the TRDGRAi register.
The PWM output pin holds level after output change by compare
match.
the TRDGRji register.)
Either 1 pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi
pin.
Forced Cutoff.)
n+1
m+1
m-n
Specification
(When “L” is selected as the active level)
14. Timers