R5F212A8SNFP#U0 Renesas Electronics America, R5F212A8SNFP#U0 Datasheet - Page 244

• Manufacturer Part Number: R5F212A8SNFP#U0
• Description: IC R8C/2A MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 14.50
Table 14.20
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
TRCGRA
TRCGRB
TRCGRC
TRCGRD
TRCGRC
TRCGRD
Timer RC Control Register 1
Register
b7 b6 b5 b4
NOTES:
1.
2.
Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
TRCCR1 register is set.
Nov 26, 2007
If the pin function is set for w aveform output (refer to Tables 7.43 to 7.50 ), the initial output level is output w hen the
b3 b2
−
BFC = 0
BFD = 0
BFC = 1
BFD = 1
TRCCR1 Register for Output Compare Function
Functions of TRCGRj Register when Using Output Compare Function
b1 b0
Setting
Bit Symbol
TRCCR1
Symbol
CCLR
TCK0
TCK1
TCK2
TOA
TOB
TOC
TOD
Page 222 of 580
General register. Write a compare value to one of these
registers.
General register. Write a compare value to one of these
registers.
Buffer register. Write the next compare value to one of
these registers. (Refer to 14.3.3.2 Buffer Operation.)
TRCIOA output level select bit
TRCIOB output level select bit
TRCIOC output level select bit
TRCIOD output level select bit
Count source select bits
TRC counter clear select bit
Address
Bit Name
0121h
Register Function
(1)
(1, 2)
(1, 2)
(1, 2)
(1, 2)
b6 b5 b4
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRCCLK input rising edge
1 1 0 : fOCO40M
1 1 1 : Do not set.
0 : Initial output “L”
1 : Initial output “H”
0 : Disable clear (free-running
1 : Clear by compare match in the
TRCGRA register
operation)
After Reset
Function
00h
TRCIOA
TRCIOB
TRCIOC
TRCIOD
TRCIOA
TRCIOB
Output Compare
Output Pin
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW