R5F212A8SNFP#U0 Renesas Electronics America, R5F212A8SNFP#U0 Datasheet - Page 464
R5F212A8SNFP#U0
Manufacturer Part Number
R5F212A8SNFP#U0
Description
IC R8C/2A MCU FLASH 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/2Ar
Specifications of R5F212A8SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
16.3.3.4
In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive
clock and returns an acknowledge signal.
Figures 16.39 and 16.40 show the Operating Timing in Slave Transmit Mode (I
The transmit procedure and operation in slave transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
(3) When the TDRE bit in the ICDRT register is set to 1 after writing the last transmit data to the ICDRT
(4) The SCL signal is released by setting the TRS bit to 0 and performing a dummy read of the ICDRR
(5) Set the TDRE bit to 0.
Nov 26, 2007
ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in
the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock
cycle. At this time, if the 8th bit of data (R/W) is 1, bits TRS and TDRE in the ICSR register are set to 1,
and the mode is switched to slave transmit mode automatically. Continuous transmission is enabled by
writing transmit data to the ICDRT register every time the TDRE bit is set to 1.
register, wait until the TEND bit in the ICSR register is set to 1 while the TDRE bit is set to 1. When the
TEND bit is set to 1, set the TEND bit to 0.
register to end the process.
Slave Transmit Operation
Page 442 of 580
16. Clock Synchronous Serial Interface
2
C bus Interface Mode).
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