MC9S08LC36LH Freescale Semiconductor, MC9S08LC36LH Datasheet - Page 159

• Manufacturer Part Number: MC9S08LC36LH
• Description: IC MCU 36K FLASH 2K RAM 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08LC36LH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 36KB (36K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 2x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: S08LC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2.5 KB
• Interface Type: I2C/SCI/SPI1/SPI2
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 18
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2-ch x 12-bit
• For Use With: DEMO9S08LC60 - BOARD DEMO FOR 9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.5.2.2
Example 2 LCD setup requirements are reiterated in the following table:
Table 9-23
Freescale Semiconductor
LCDSUPPLY
XXXXXX01
1XXXXX01
LCDCLKS
0X011X11
10000010
Example
Register
LCDCR1
LCDCR0
2
lists the required setup values required to initialize the LCD as specified by Example 2:
Operating
Voltage,
Initialization
VSUPPLY[1:0]
CPCADJ[1:0]
CLKADJ[5:0]
3.6-V
Bit/bit field
LCDCPMS
LCDCPEN
HDRVBUF
V
DUTY[1:0]
BBYPASS
LCDSTP3
LCLK[2:0]
SOURCE
LPWAVE
LCDWAI
DD
DIV16
LCD Clock
100 kHz
Source
Internal
Table 9-23. Initialization Register Values for Example 2
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
000010
Binary
Value
011
Example 2
XX
01
10
X
X
X
X
1
0
1
0
1
LCD Glass
Operating
Voltage
3-V
Selects the bus clock as the LCD clock input
External clock reference = 0; Bus clock = 1
Adjusts the LCD clock input (see table 9-12)
Adjusts the LCD clock input (see table 9-12)
Enable the charge pump
Don’t care since power is from internal V
Doubler mode = 0; Tripler mode = 1
High drive buffer
Configure LCD charge pump clock source
Buffer Bypass; Buffer mode = 0; Unbuffered mode = 1
Power LCD via V
V
LCD is “on” in WAIT mode
LCD is “off” in STOP3 mode
For 1/3 duty cycle, select closest value to the desired 80 Hz LCD frame frequency
(see table 9-13). Note the LCD base frequency - 256.2 Hz
Low power waveform
For 99 segments (3x33), select 1/3 duty cycle (see table 9-11)
LL3
is generated from V
segments
Required
LCD
99
DD
internal power (see table 9-16). When VSUPPLY[1:0] = 01,
Frame
80 Hz Individual segment
Rate
LCD
DD .
Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
Mode/Rate
Comment
Blinking
0.5 Hz
DD
WAIT modes
Behavior in
STOP3 and
STOP3: off
WAIT: on
LCD Power
Power via
Input
V
DD
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