MC9S08LC36LH Freescale Semiconductor, MC9S08LC36LH Datasheet - Page 133

• Manufacturer Part Number: MC9S08LC36LH
• Description: IC MCU 36K FLASH 2K RAM 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08LC36LH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 36KB (36K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 2x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: S08LC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2.5 KB
• Interface Type: I2C/SCI/SPI1/SPI2
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 18
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2-ch x 12-bit
• For Use With: DEMO9S08LC60 - BOARD DEMO FOR 9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.3.4.1
If LCDDRMS bit in the LCDCMD register is deasserted, the LCDRAM register accesses a register bank
that controls the on/off state for frontplane drivers.
9.3.4.2
If LCDDRMS in the LCDCMD register is asserted, the LCDRAM register accesses a register bank that
controls the blink enables/disables for each individual LCD segment
9.3.5
Read: anytime
Write: anytime.It is recommended that CLKADJ[5:0], DIV16, and SOURCE not be modified while the
LCDEN bit is asserted.
Freescale Semiconductor
FP[n]BP[x]
FP[n]BP[x]
Reset
Field
Field
W
R
SOURCE
LCD Clock Source Register (LCDCLKS)
Segment On — If LCDDRMS in the LCDCMD is deasserted (LCDDRMS=0), the FP[n]BP[x] bit in the LCDRAM
registers controls on/off state for the LCD segment connected between FP[n] and BP[x].Asserting the FP[n]BP[x]
bit displays (turns on) the LCD segment connected between FP[n] and BP[x].
0 LCD segment off.
1 LCD segment on.
LCD Segment Blink Enable — If LCDDRMS bit in the LCDCMD is asserted (LCDDRMS=1), the FP[n]BP[x] bit
in the LCDRAM registers controls blink mode enable/disable state for the LCD segment connected between
FP[n] and BP[x].Asserting the FP[n]BP[x] bit enable the blink mode for the LCD segment connected between
FP[n] and BP[x] if the associated bit when LCDDRMS = 0 is also set.
0 Disables blink enable for LCD segment.
1 Enables blink enable for LCD segment.
LCDRAM Registers as On/Off Selector (LCDDRMS = 0)
LCDRAM Registers as Blink Enable/Disable (LCDDRMS = 1)
0
7
Table 9-7. LCDRAM Field Descriptions (when LCDDRMS = 0)
Table 9-8. LCDRAM Field Descriptions (when LCCDRMS = 1)
DIV16
0
6
Figure 9-6. LCD Clock Source Register (LCDCLKS)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
CLKADJ5
0
5
CLKADJ4
0
4
Description
Description
CLKADJ3
3
0
Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
.
CLKADJ2
1
2
CLKADJ1
0
1
CLKADJ0
1
0
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