MC9S08LC36LH Freescale Semiconductor, MC9S08LC36LH Datasheet - Page 122

IC MCU 36K FLASH 2K RAM 64-LQFP

MC9S08LC36LH

Manufacturer Part Number
MC9S08LC36LH
Description
IC MCU 36K FLASH 2K RAM 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets

Specifications of MC9S08LC36LH

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LCD, LVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
36KB (36K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 2x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
64-LQFP
Processor Series
S08LC
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
I2C/SCI/SPI1/SPI2
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
18
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Minimum Operating Temperature
- 40 C
On-chip Adc
2-ch x 12-bit
For Use With
DEMO9S08LC60 - BOARD DEMO FOR 9S08LC60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08LC36LH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
INH
IMM
DIR
EXT
DD
IX+D
Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E)
Chapter 8 Central Processor Unit (S08CPUV2)
122
Bit-Manipulation
Inherent
Immediate
Direct
Extended
DIR to DIR
IX+ to DIR
Branch
REL
IX
IX1
IX2
IMD
DIX+
Relative
Indexed, No Offset
Indexed, 8-Bit Offset
Indexed, 16-Bit Offset
IMM to DIR
DIR to IX+
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Read-Modify-Write
Table 8-3. Opcode Map (Sheet 2 of 2)
SP1
SP2
IX+
IX1+
9E60
3
9E61
4
9E63
3
9E64
3
9E66
3
9E67
3
9E68
3
9E69
3
9E6A
3
9E6B
4
9E6C
3
9E6D
3
9E6F
3
Stack Pointer, 8-Bit Offset
Stack Pointer, 16-Bit Offset
Indexed, No Offset with
Post Increment
Indexed, 1-Byte Offset with
Post Increment
CBEQ
DBNZ
COM
NEG
ROR
DEC
LSR
ASR
ROL
CLR
LSL
TST
INC
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
6
6
6
6
6
6
6
6
6
8
6
5
6
Control
Prebyte (9E) and Opcode in
9EAE
2
LDHX
Number of Bytes
IX
5
Hexadecimal
9EBE
4
LDHX
IX2
6
9ECE
3
9E60
3
LDHX
Register/Memory
NEG
SP1
IX1
Freescale Semiconductor
5
6
9ED0
4
9ED1
4
9ED2
4
9ED3
4
9ED4
4
9ED5
4
9ED6
4
9ED7
4
9ED8
4
9ED9
4
9EDA
4
9EDB
4
9EDE
4
9EDF
4
HCS08 Cycles
Instruction Mnemonic
Addressing Mode
CMP
SUB
SBC
CPX
AND
EOR
ADC
ORA
ADD
LDA
LDX
STX
STA
BIT
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
9EE0
3
9EE1
3
9EE2
3
9EE3
3
9EE4
3
9EE5
3
9EE6
3
9EE7
3
9EE8
3
9EE9
3
9EEA
3
9EEB
3
9EEE
3
9EEF
3
CMP
EOR
ORA
SUB
SBC
CPX
AND
ADC
ADD
LDA
STA
LDX
STX
BIT
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
9EF3
3
9EFE
3
9EFF
3
CPHX
LDHX
STHX
SP1
SP1
SP1
6
5
5

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