MC9S08LC36LH Freescale Semiconductor, MC9S08LC36LH Datasheet - Page 155

• Manufacturer Part Number: MC9S08LC36LH
• Description: IC MCU 36K FLASH 2K RAM 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08LC36LH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 36KB (36K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 2x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: S08LC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2.5 KB
• Interface Type: I2C/SCI/SPI1/SPI2
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 18
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2-ch x 12-bit
• For Use With: DEMO9S08LC60 - BOARD DEMO FOR 9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.4.5
During a reset, the LCD module system is configured in the default mode. The default mode includes the
following settings:
9.4.6
When an LCD module frame (LPWAVE = 0) or sub-frame (LPWAVE = 1) frequency interrupt event
occurs, the LCDIF bit in the LCDCMD register is asserted. The LCDIF bit remains asserted until the LCD
module frame frequency interrupt is cleared by software. The interrupt can be cleared by software by
writing a 1 to the LCDIF bit.
If a both the LCDIF bit in the LCDCMD register and the LCDIEN bit in the LCDCR1 register are set, an
LCD interrupt signal asserts.
For both normal waveform and low-power waveform, configured for the same frequency with the same
clock configuration. The low-power waveform splits a frame into two subframes with equal duration. See
Figure 9-11
When an LCD module frame(LPWAVE=0) or sub-frame(LPWAVE=1) frequency interrupt event occurs,
the LCDIF bit in the LCDCMD register is asserted. The LCDIF bit remains asserted until the LCD module
frame frequency interrupt is cleared by software. The interrupt can be cleared by software by writing a 1
to the LCDIF bit.
9.5
This section provides a recommended initialization sequence for the LCD module and also includes
initialization examples for several possible LCD application scenarios.
Freescale Semiconductor
•
•
•
•
•
VSUPPLY[1:0]
LCDEN is cleared, thereby forcing all frontplane and backplane driver outputs to the high
impedance state.
1/4 duty
1/3 bias
All frontplane enable bits, FP[n]EN, are cleared
LCLK[2:0], VSUPPLY[2:0], BBYPASS, and BRATE[2:0] revert to their reset values
Initialization Section
00
01
Resets
Interrupts
through
V
V
Figure
LL2
LL3
is generated from V
is generated from V
9-16.
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
V
DD
Switch Option
Table 9-20. V
DD
DD
DD
Switch Option
Recommend Use for 3-V
• V
• V
• V
• V
• V
• V
LL1
DD
LL3
LL1
LL2
DD
LCD Panels
= V
= V
= 1v
= 1v
= 2v
= 3v
Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
LL2
LL3
= 2v
= 3v
Recommend Use for 5-V
Invalid LCD power
configuration
• V
• V
• V
LL1
DD
LL3
LCD Panels
= V
= 1.67v
= 5v
LL2
= 3.3v
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