C8051F501-IQ Silicon Laboratories Inc, C8051F501-IQ Datasheet - Page 193

• Manufacturer Part Number: C8051F501-IQ
• Description: IC 8051 MCU 64K FLASH 48-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F501-IQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 48-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Package: 48PQFP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1512

SFR Definition 20.15. P0SKIP: Port 0 Skip
SFR Address = 0xD4; SFR Page = 0x0F
SFR Definition 20.16. P1: Port 1
SFR Address = 0x90; SFR Page = All Pages; Bit-Addressable
Name
Reset
Name
Reset
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
P0SKIP[7:0]
P1[7:0]
Name
Name
7
0
7
1
Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
6
0
6
1
Description
5
0
5
1
Rev. 1.2
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
0
4
1
P0SKIP[7:0]
P1[7:0]
R/W
R/W
Function
Write
3
0
3
1
C8051F50x/F51x
2
0
2
1
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
1
0
1
1
Read
0
0
0
1
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