C8051F501-IQ Silicon Laboratories Inc, C8051F501-IQ Datasheet
C8051F501-IQ
Manufacturer Part Number
C8051F501-IQ
Description
IC 8051 MCU 64K FLASH 48-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F501-IQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
48-QFP
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
32-ch x 12-bit
Package
48PQFP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1527 - KIT DEV FOR C8051F50X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1512
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F501-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F501-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Analog Peripherals
12-Bit ADC, 5 V input signal; up to 32 external inputs
-
-
-
-
Built-in Temperature Sensor (±3 °C)
Two Comparators
Precision Internal Voltage Reference
V
On-Chip Debug
-
-
-
-
Temperature Range: –40 to +125 °C
Operating Voltage: 1.8 to 5.25 V
-
Development Kit: C8051F500DK
Automotive
DD
±1 LSB INL; guaranteed monotonic
Programmable throughput up to 200 ksps
Data-dependent windowed interrupt generator
Programmable gain maximizes input signal span
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watch-points
Inspect/modify memory, registers, and stack
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Multiple power saving sleep and shutdown modes
Monitor/Brown-out Detector
C2CK/RST
VREGIN
GNDA
VDDA
GND
VDD
C2D
Internal Oscillator
Programming
Power On
Hardware
Voltage Regulator
Debug /
Reset
(±0.5%)
System Clock Setup
(LDO)
Reset
Clock Multiplier
CIP-51 8051 Controller
50 MIPS, 64 kB Flash, 12-Bit ADC, 48-Pin Automotive MCU
Copyright © 2008 by Silicon Laboratories
64 kB Flash Program
External Oscillator
XTAL1
Core (50 MHz)
256 Byte RAM
4 kB XRAM
Memory
XTAL2
SFR
Bus
High-Speed 8051 µC Core
-
-
Memory
-
-
Digital Peripherals
-
-
-
-
-
Clock Sources
-
-
Ordering Part Numbers
-
-
Pipelined instruction architecture; executes 70% of instructions in one or
two system clocks
Up to 50 MIPS throughput
64 kB Flash; in-system programmable; flexible security features
4352 bytes data RAM (256 + 4 kB)
Up to 40 digital I/O; all are 5 V push-pull
Hardware I
Programmable 16-bit counter array with six capture/compare modules
Four general-purpose 16-bit counter/timers
External Memory Interface (EMIF)
Internal programmable ±0.5% oscillator: up to 50 MHz
External oscillator: Crystal, RC, C, or CMOS Clock
C8051F501-IM, 48-Pin QFN (RoHS-compliant), 7 x 7 mm
C8051F501-IQ, 48-Pin QFP (RoHS-compliant), 9 x 9 mm
VDD
PCA/WDT
Timers 0,
6 channel
External Memory Interface
UART0
1, 2, 3
12-bit
200ksps
ADC
Analog Peripherals
Digital Peripherals
SPI
I2C
Port I/O Configuration
Crossbar Control
Reference
Voltage
CP0, CP0A
CP1, CP1A
Comparator 0
Comparator 1
VREF
2
C, SPI™, and UART serial ports available concurrently
M
A
U
X
VREF
Crossbar
Decoder
Priority
+
+
-
-
VDD
VREF
P0 – P3
Temp
Sensor
GND
Drivers
Drivers
Drivers
Drivers
Drivers
Port 0
Port 1
Port 2
Port 3
Port 4
C8051F501
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
VIO
2
2
11.20.2008
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