C8051F501-IQ Silicon Laboratories Inc, C8051F501-IQ Datasheet - Page 14

• Manufacturer Part Number: C8051F501-IQ
• Description: IC 8051 MCU 64K FLASH 48-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F501-IQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 48-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Package: 48PQFP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1512

C8051F50x/F51x
SFR Definition 17.2. RSTSRC: Reset Source ............................................................ 146
SFR Definition 18.1. EMI0CN: External Memory Interface Control ............................ 151
SFR Definition 18.2. EMI0CF: External Memory Configuration .................................. 152
SFR Definition 18.3. EMI0TC: External Memory Timing Control ................................ 157
SFR Definition 19.1. CLKSEL: Clock Select ............................................................... 166
SFR Definition 19.2. OSCICN: Internal Oscillator Control .......................................... 168
SFR Definition 19.3. OSCICRS: Internal Oscillator Coarse Calibration ...................... 169
SFR Definition 19.4. OSCIFIN: Internal Oscillator Fine Calibration ............................ 169
SFR Definition 19.5. CLKMUL: Clock Multiplier .......................................................... 171
SFR Definition 19.6. OSCXCN: External Oscillator Control ........................................ 173
SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0 .......................................... 184
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 .......................................... 185
SFR Definition 20.3. XBR2: Port I/O Crossbar Register 1 .......................................... 186
SFR Definition 20.4. P0MASK: Port 0 Mask Register ................................................. 187
SFR Definition 20.5. P0MAT: Port 0 Match Register .................................................. 187
SFR Definition 20.6. P1MASK: Port 1 Mask Register ................................................. 188
SFR Definition 20.7. P1MAT: Port 1 Match Register .................................................. 188
SFR Definition 20.8. P2MASK: Port 2 Mask Register ................................................. 189
SFR Definition 20.9. P2MAT: Port 2 Match Register .................................................. 189
SFR Definition 20.10. P3MASK: Port 3 Mask Register ............................................... 190
SFR Definition 20.11. P3MAT: Port 3 Match Register ................................................ 190
SFR Definition 20.12. P0: Port 0 ................................................................................. 191
SFR Definition 20.13. P0MDIN: Port 0 Input Mode ..................................................... 192
SFR Definition 20.14. P0MDOUT: Port 0 Output Mode .............................................. 192
SFR Definition 20.15. P0SKIP: Port 0 Skip ................................................................. 193
SFR Definition 20.16. P1: Port 1 ................................................................................. 193
SFR Definition 20.17. P1MDIN: Port 1 Input Mode ..................................................... 194
SFR Definition 20.18. P1MDOUT: Port 1 Output Mode .............................................. 194
SFR Definition 20.19. P1SKIP: Port 1 Skip ................................................................. 195
SFR Definition 20.20. P2: Port 2 ................................................................................. 195
SFR Definition 20.21. P2MDIN: Port 2 Input Mode ..................................................... 196
SFR Definition 20.22. P2MDOUT: Port 2 Output Mode .............................................. 196
SFR Definition 20.23. P2SKIP: Port 2 Skip ................................................................. 197
SFR Definition 20.24. P3: Port 3 ................................................................................. 197
SFR Definition 20.25. P3MDIN: Port 3 Input Mode ..................................................... 198
SFR Definition 20.26. P3MDOUT: Port 3 Output Mode .............................................. 198
SFR Definition 20.27. P3SKIP: Port 3Skip .................................................................. 199
SFR Definition 20.28. P4: Port 4 ................................................................................. 199
SFR Definition 20.29. P4MDOUT: Port 4 Output Mode .............................................. 200
SFR Definition 21.1. LIN0ADR: LIN0 Indirect Address Register ................................. 208
SFR Definition 21.2. LIN0DAT: LIN0 Indirect Data Register ....................................... 208
SFR Definition 21.3. LIN0CF: LIN0 Control Mode Register ........................................ 209
SFR Definition 22.1. CAN0CFG: CAN Clock Configuration ........................................ 225
SFR Definition 23.1. SMB0CF: SMBus Clock/Configuration ...................................... 232
SFR Definition 23.2. SMB0CN: SMBus Control .......................................................... 234
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