C8051F501-IQ Silicon Laboratories Inc, C8051F501-IQ Datasheet - Page 166

• Manufacturer Part Number: C8051F501-IQ
• Description: IC 8051 MCU 64K FLASH 48-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F501-IQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 48-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Package: 48PQFP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1512

C8051F50x/F51x
SFR Definition 19.1. CLKSEL: Clock Select
SFR Address = 0x8F; SFR Page = 0x0F;
Important Note: If the selected system clock is greater than 25 MHz, please be aware of the following:
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166
Name
Reset
7:2
1:0
Bit
Type
Bit
Flash Scale Timing must be configured for the faster system clock. See SFR Definition 15.3 for more
details.
VDD and VDDA voltage must be 2 V or higher.
It is recommended to enable the VDD monitor as a reset source and configure it for the high threshold.
See SFR Definition 17.1 for details on configuring the VDD monitor. If the VDD monitor is configured to
the high threshold, the VDD and VDDA voltage must be greater than the VDD monitor high threshold.
See Table 5.4 for VDD monitor threshold specifications.
CLKSL[1:0] System Clock Source Select Bits.
Unused
Name
R
7
0
Read = 000000b; Write = Don’t Care
00: SYSCLK derived from the Internal Oscillator and scaled per the IFCN bits in reg-
ister OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the Clock Multiplier.
11: reserved.
R
6
0
R
5
0
Rev. 1.2
R
4
0
Function
R
3
0
R
2
0
1
0
CLKSL[1:0]
R/W
0
0