C8051F501-IQ Silicon Laboratories Inc, C8051F501-IQ Datasheet - Page 147

IC 8051 MCU 64K FLASH 48-QFP

C8051F501-IQ

Manufacturer Part Number
C8051F501-IQ
Description
IC 8051 MCU 64K FLASH 48-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Datasheets

Specifications of C8051F501-IQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
48-QFP
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
32-ch x 12-bit
Package
48PQFP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1527 - KIT DEV FOR C8051F50X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1512

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F501-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F501-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
18. External Data Memory Interface and On-Chip XRAM
For C8051F50x/F51x devices, 4 kB of RAM are included on-chip and mapped into the external data mem-
ory space (XRAM). Additionally, an External Memory Interface (EMIF) is available on the C8051F500/1/4/5
and C8051F508/9-F510/1 devices, which can be used to access off-chip data memories and memory-
mapped devices connected to the GPIO ports. The external memory space may be accessed using the
external move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect addressing
mode using R0 or R1. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then
the high byte of the 16-bit address is provided by the External Memory Interface Control Register
(EMI0CN, shown in SFR Definition 18.1).
Note: The MOVX instruction can also be used for writing to the Flash memory. See Section “
18.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The sec-
ond method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
18.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
18.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
page
MOV
MOVX
MOV
MOV
MOVX
129
for details. The MOVX instruction accesses XRAM by default.
DPTR, #1234h
A, @DPTR
EMI0CN, #12h
R0, #34h
a, @R0
; load DPTR with 16-bit address to read (0x1234)
; load contents of 0x1234 into accumulator A
; load high byte of address into EMI0CN
; load low byte of address into R0 (or R1)
; load contents of 0x1234 into accumulator A
Rev. 1.2
C8051F50x/F51x
15. Flash Memory
” on
147

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