AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 943

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6438F–ATARM–21-Jun-10
Figure 40-4. Touch Screen Pen Detect
The Touch Screen Pen Detect can be used to generate a TSADCC interrupt to wake up the sys-
tem or it can be programmed to trig a conversion, so that a position can be measured as soon as
a contact is detected if the TSADCC is programmed for an operating mode involving the Touch
Screen.
The Pen Detect generates two types of status, reported in the
Both bits are automatically cleared as soon as the Status Register TSADCC_SR is read, and
can generate an interrupt by writing accordingly the
• the bit PENCNT is set as soon as a current flows for a time over the debouncing time as
• the bit NOCNT is set as soon as no current flows for a time over the debouncing time as
defined by PENDBC and remains set until TSADCC_SR is read.
defined by PENDBC and remains set until TSADCC_SR is read.
X
Y
X
Y
M
M
P
P
VDDANA
VDDANA
GND
GND
GND
“TSADCC Interrupt Enable
To the ADC
“TSADCC Status
Debouncer
PENDBC
AT91SAM9G45
Pen Interrupt
Register”.
Register”:
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