AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 164

MCU ARM9 324-TFBGA

AT91SAM9G45-CU

Manufacturer Part Number
AT91SAM9G45-CU
Description
MCU ARM9 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM9G45-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
800 MHz
Number Of Programmable I/os
160
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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20.2.5
20.2.5.1
Table 20-4.
Notes:
164
Signals:
EBI_
Controller
D0 - D7
D8 - D15
D16 - D23
D24 - D31
A0/NBS0
A1/NWR2/NBS2
A2 - A22
A23 - A25
NCS0
NCS1/DDRSDCS
NCS2
NCS3/NANDCS
NCS4/CFCS0
NCS5/CFCS1
NRD/CFOE
NWR0/NWE
NWR1/NBS1
NWR3/NBS3
1. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
2. NWRx enables corresponding byte x writes. (x = 0,1,2 or 3)
3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
(5)
AT91SAM9G45
Application Example
Hardware Interface
EBI Pins and External Static Devices Connections
8-bit Static
A[23:25]
Device
D0 - D7
A[2:22]
Table 20-4 on page 164
external devices for each Memory Controller.
WE
OE
CS
CS
CS
CS
CS
CS
A0
A1
2 x 8-bit
Devices
D8 - D15
A[22:24]
D0 - D7
A[1:21]
Static
WE
WE
CS
CS
CS
CS
CS
CS
OE
A0
(1)
(1)
details the connections to be applied between the EBI pins and the
16-bit Static
Pins of the Interfaced Device
D8 - D15
A[22:24]
Device
D0 - D7
A[1:21]
NUB
NLB
WE
CS
CS
CS
CS
CS
CS
OE
A0
SMC
D16 - D23
D24 - D31
4 x 8-bit
D8 - D15
Devices
A[21:23]
D0 - D7
A[0:20]
Static
WE
WE
WE
WE
CS
CS
CS
CS
OE
CS
CS
(2)
(2)
(2)
(2)
2 x 16-bit
D16 - D23
D24 - D31
Devices
A[21:23]
D0 - D7
D8 - 15
A[0:20]
NUB
NUB
Static
NLB
NLB
WE
CS
CS
CS
CS
CS
CS
OE
(3)
(4)
(3)
(4)
6438F–ATARM–21-Jun-10
32-bit Static
D16 - D23
D24 - D31
A[21:23]
D0 - D7
Device
D8 - 15
A[0:20]
BE0
BE2
BE1
BE3
WE
CS
CS
CS
CS
CS
CS
OE

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