AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 600

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

33.7.8.6
Figure 33-41. Header Reception
6438F–ATARM–21-Jun-10
te RSTSTA=1
Baud Rate
US_LINIR
in US_CR
LINBK
LINID
Clock
RXD
Header Reception (Slave Node Configuration)
All the LIN Frames start with a header which is sent by the master node and consists of a Synch
Break Field, Synch Field and Identifier Field.
In Slave node configuration, the frame handling starts with the reception of the header.
The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At
any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break
Field. As long as a Break Field has not been detected, the USART stays idle and the received
data are not taken in account.
When a Break Field has been detected, the flag LINBK in the Channel Status register
(US_CSR) is set to “1” and the USART expects the Synch Field character to be 0x55. This field
is used to update the actual baud rate in order to stay synchronized (see
received Synch character is not 0x55, an Inconsistent Synch Field error is generated (see
tion
After receiving the Synch Field, the USART expects to receive the Identifier Field.
When the Identifier Field has been received, the flag LINID in the Channel Status register
(US_CSR) is set to “1”. At this moment the field IDCHR in the LIN Identifier register (US_LINIR)
is updated with the received character. The Identifier parity bits can be automatically computed
and checked (see
STA at “1” in the Control register (US_CR).
13 dominant bits (at 0)
33.7.8.13).
Break Field
Section
1 recessive bit
Delimiter
Break
(at 1)
33.7.8.8).The flags LINID and LINBK are reset by writing the bit RST-
Start
Bit
1
0
Synch Byte = 0x55
1
0
1
0
1
0
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
AT91SAM9G45
Section
33.7.8.7). If the
Stop
Bit
Sec-
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