AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 6

MCU ARM9 324-TFBGA

AT91SAM9G45-CU

Manufacturer Part Number
AT91SAM9G45-CU
Description
MCU ARM9 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM9G45-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
800 MHz
Number Of Programmable I/os
160
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Table 3-1.
6
Signal Name
PD0 - PD31
PE0 - PE31
DDR_D0 -
DDR_D15
DDR_A0 -
DDR_A13
DDR_CLK-
#DDR_CLK
DDR_CKE
DDR_CS
DDR_WE
DDR_RAS-
DDR_CAS
DDR_DQM[0..1]
DDR_DQS[0..1]
DDR_BA0 -
DDR_BA1
DDR_VREF
D0 -D31
A0 - A25
NWAIT
NCS0 - NCS5
NWR0 - NWR3
NRD
NWE
NBS0 - NBS3
CFCE1 - CFCE2
CFOE
CFWE
CFIOR
CFIOW
CFRNW
AT91SAM9G45
Signal Description List (Continued)
Parallel IO Controller D
Parallel IO Controller E
Data Bus
Address Bus
DDR differential clock input
DDR Clock Enable
DDR Chip Select
DDR Write Enable
Row and Column Signal
Write Data Mask
Data Strobe
Bank Select
Reference Voltage
Data Bus
External Wait Signal
Chip Select Lines
Write Signal
Read Signal
Write Enable
Byte Mask Signal
CompactFlash Chip Enable
CompactFlash Output Enable
CompactFlash Write Enable
CompactFlash IO Read
CompactFlash IO Write
CompactFlash Read Not Write
Address Bus
Function
DDR Memory Interface- DDR2/SDRAM/LPDDR Controller
Static Memory Controller - SMC
External Bus Interface - EBI
CompactFlash Support
I/O
I/O
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
I/O
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Active
Level
Reference
(1)
(1)
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
Voltage
0 at reset
Comments
Pulled-up input at reset
(100k
Pulled-up input at reset
(100k
Pulled-up input at reset
Pulled-up input at reset
0 at reset
)
)
(3)
(3)
, Schmitt trigger
, Schmitt trigger
6438F–ATARM–21-Jun-10

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