AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 1197

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

49.2.4
49.2.4.1
49.2.5
49.2.5.1
49.2.5.2
49.2.6
49.2.6.1
6438F–ATARM–21-Jun-10
Static Memory Controller (SMC)
Serial Synchronous Controller (SSC)
Touch Screen (TSADCC)
SMC Delay: Access
SSC: Data sent without any frame synchro
SSC: Unexpected delay on TD output
TSADCC: Pen detect accuracy is not good
In this document, the Access is “Read-write” in the Register Mapping Table (SMC_DELAY1 to
SMC_DELAY8 rows), and in the SMC DELAY I/O Register.
The current access is “Write-only”.
None
When SSC is configured with the following conditions:
The data is sent but there is not any toggle of the TF line
Transmit STTDLY must be different from 0.
When SSC is configured with the following conditions:
Unexpected delay of 2 or 3 system clock cycles is added to TD output.
None
Depending on LCD panels, the pen detect is noisy, leading to an unpredictable behavior.
An additional resistor solves the problem. Its value (between 100 kOhm and 250 kOhm) is to be
tuned for the LCD panel.
• RF is in input,
• TD is synchronized on a receive START (any condition: START field = 2 to 7)
• TF toggles at each start of data transfer
• Transmit STTDLY = 0
• Check TD and TF after a receive START,
• TCMR.STTDLY more than 0
• RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge
• RFMR.FSOS = None (input)
• TCMR.START = Receive Start
Problem/Fix Workaround
Problem/Fix Workaround
Problem/Fix Workaround
Problem/Fix Workaround
AT91SAM9G45
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