AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 762

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

36.6
36.6.1
36.6.2
36.6.3
6438F–ATARM–21-Jun-10
Product Dependencies
I/O Lines
Power Management
Interrupt
The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with
PIO lines. The programmer must first program the PIO controllers to assign the peripheral func-
tions to HSMCI pins.
Table 36-2.
The HSMCI is clocked through the Power Management Controller (PMC), so the programmer
must first configure the PMC to enable the HSMCI clock.
The HSMCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling the HSMCI interrupt requires programming the AIC before configuring the HSMCI.
Table 36-3.
Instance
HSMCI0
HSMCI1
Instance
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
I/O Lines
Peripheral IDs
11
29
ID
MCI0_CDA
MCI1_CDA
MCI0_DA0
MCI0_DA1
MCI0_DA2
MCI0_DA3
MCI0_DA4
MCI0_DA5
MCI0_DA6
MCI0_DA7
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI1_DA4
MCI1_DA5
MCI1_DA6
MCI1_DA7
MCI0_CK
MCI1_CK
Signal
I/O Line
PA22
PA31
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
AT91SAM9G45
PA1
PA0
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
Peripheral
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
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