PIC18F45J50-I/PT Microchip Technology, PIC18F45J50-I/PT Datasheet - Page 52

• Manufacturer Part Number: PIC18F45J50-I/PT
• Description: IC PIC MCU FLASH 32K 2V 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45J50-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 2.25 V to 2.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3776Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Embedded Interface Type: EUSART, I2C, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F46J50 FAMILY
REGISTER 3-3:
REGISTER 3-4:
DS39931C-page 52
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
Sleep or the device is in Deep Sleep and the dedicated DSBOR is enabled and V
DSBOR threshold, or DSBOR is enabled or disabled, but V
Sleep or the device is in Deep Sleep and the dedicated DSBOR is enabled and V
DSBOR threshold, or DSBOR is enabled or disabled, but V
All register bits are maintained unless: V
All register bits are maintained unless: V
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0
(BANKED F4Eh)
DSGPR1: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 1
(BANKED F4Fh)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
Deep Sleep Persistent General Purpose bits
Deep Sleep Persistent General Purpose bits
DDCORE
DDCORE
R/W-xxxx
R/W-xxxx
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
drops below the normal BOR threshold outside of Deep
drops below the normal BOR threshold outside of Deep
(1)
(1)
DD
DD
is hard cycled to near V
is hard cycled to near V
© 2009 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
DD
DD
drops below the
drops below the
SS
SS
.
.
bit 0
bit 0