PIC18F45J50-I/PT Microchip Technology, PIC18F45J50-I/PT Datasheet - Page 261

• Manufacturer Part Number: PIC18F45J50-I/PT
• Description: IC PIC MCU FLASH 32K 2V 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45J50-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 2.25 V to 2.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3776Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Embedded Interface Type: EUSART, I2C, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.5.8
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCPx pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCPx module without change.
17.5.8.1
If the Fail-Safe Clock Monitor (FSCM) is enabled, a
clock
power-managed RC_RUN mode and the OSCFIF bit of
TABLE 17-5:
© 2009 Microchip Technology Inc.
INTCON
RCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
TRISC
TMR1L
TMR1H
T1CON
TMR2
T2CON
PR2
TMR3L
TMR3H
T3CON
CCPR1L
CCPR1H
CCP1CON
ECCP1AS
ECCP1DEL
Legend:
Note 1:
Name
failure
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
These bits are only available on 44-pin devices.
OPERATION IN POWER-MANAGED
MODES
Timer1 Register Low Byte
Timer1 Register High Byte
Timer2 Register
Timer2 Period Register
Timer3 Register Low Byte
Timer3 Register High Byte
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0
Operation with Fail-Safe
Clock Monitor (FSCM)
TMR1CS1
TMR3CS1
GIE/GIEH
PMPIF
PMPIE
PMPIP
P1RSEN
OSCFIE
OSCFIP
OSCFIF
TRISC7
P1M1
IPEN
Bit 7
will
—
REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
(1)
(1)
(1)
force
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
PEIE/GIEL
TMR1CS0
TMR3CS0
SBOREN
TRISC6
P1DC6
CM2IE
CM2IP
CM2IF
P1M0
ADIE
ADIP
Bit 6
ADIF
the
device
T1CKPS1
T3CKPS1
TMR0IE
TRISC5
DC1B1
P1DC5
CM1IF
CM1IE
CM1IP
RCIF
RCIE
RCIP
Bit 5
—
into
the
T1CKPS0
T3CKPS0
TRISC4
DC1B0
P1DC4
INT0IE
USBIF
USBIE
USBIP
TXIE
TXIP
Bit 4
TXIF
RI
PIC18F46J50 FAMILY
the PIR2 register will be set. The ECCPx will then be
clocked from the internal oscillator clock source, which
may have a different clock frequency than the primary
clock.
17.5.9
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states.
This forces the ECCP module to reset to a state
compatible
modules used on other PIC18 and PIC16 devices.
T1OSCEN
T3OSCEN
PSS1AC1
CCP1M3
BCL1IF
BCL1IE
BCL1IP
P1DC3
RABIE
SSPIE
SSPIP
SSPIF
Bit 3
TO
—
EFFECTS OF A RESET
PSS1AC0 PSS1BD1 PSS1BD0
T1SYNC
T3SYNC
CCP1M2
with
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIE
HLVDIP
TRISC2
HLVDIF
P1DC2
Bit 2
PD
previous, non-enhanced
CCP1M1
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISC1
INT0IF
P1DC1
RD16
RD16
Bit 1
POR
TMR1ON
TMR3ON
DS39931C-page 261
CCP1M0
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
TRISC0
P1DC0
RABIF
Bit 0
BOR
on page:
Values
Reset
ECCP
258
81
84
81
85
85
85
85
85
86
81
81
81
81
81
81
81
81
81
81
81
81
81