PIC18F45J50-I/PT Microchip Technology, PIC18F45J50-I/PT Datasheet - Page 301

• Manufacturer Part Number: PIC18F45J50-I/PT
• Description: IC PIC MCU FLASH 32K 2V 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45J50-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 2.25 V to 2.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3776Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Embedded Interface Type: EUSART, I2C, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.5.5
The addressing procedure for the I
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General
(SSPxCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPxSR and the address is
compared against the SSPxADD. It is also compared to
the general call address and fixed in hardware.
FIGURE 18-17:
18.5.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware if the
TRIS bits are set.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Start (S) and Stop (P) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I
the bus is Idle, with both the Start and Stop bits clear.
In Firmware Controlled Master mode, user code
conducts all I
Stop bit conditions.
© 2009 Microchip Technology Inc.
GCEN (SSPxCON2<7>)
SSPOV (SSPxCON1<6>)
SDAx
SCLx
SSPxIF
BF (SSPxSTAT<0>)
2
C bus may be taken when the Stop bit is set, or
Call
GENERAL CALL ADDRESS
SUPPORT
MASTER MODE
2
C bus operations based on Start and
Enable
S
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7-BIT OR 10-BIT ADDRESSING MODE)
bit,
1
2
GCEN,
General Call Address
2
C bus is such that
3
2
4
C protocol. It
is
5
enabled
6
7
R/W = 0
8
PIC18F46J50 FAMILY
If the general call address matches, the SSPxSR is
transferred to the SSPxBUF, the BF flag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit), the
SSPxIF interrupt flag bit is set.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPxBUF. The value can be used to determine if the
address was device-specific or a general call address.
In 10-bit mode, the SSPxADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPxSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-Bit Addressing mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 18-17).
ACK
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
Address is compared to General Call Address
after ACK, set interrupt
9
Assert a Start condition on SDAx and SCLx.
Assert a Repeated Start condition on SDAx and
SCLx.
Write to the SSPxBUF register initiating
transmission of data/address.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDAx and SCLx.
D7
1
D6
2
Cleared in software
SSPxBUF is read
Receiving Data
D5
3
D4
2
4
C port to receive data.
D3
5
D2
6
D1
7
DS39931C-page 301
D0
8
ACK
9
‘0’
‘1’