PIC18F45J50-I/PT Microchip Technology, PIC18F45J50-I/PT Datasheet - Page 50

• Manufacturer Part Number: PIC18F45J50-I/PT
• Description: IC PIC MCU FLASH 32K 2V 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45J50-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 2.25 V to 2.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3776Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Embedded Interface Type: EUSART, I2C, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F46J50 FAMILY
3.6.5
The Deep Sleep module contains a dedicated Deep Sleep
BOR (DSBOR) circuit. This circuit may be optionally
enabled through the DSBOREN Configuration bit.
The DSBOR circuit monitors the V
voltage. The behavior of the DSBOR circuit is
described in Section 4.4 “Brown-out Reset (BOR)”.
3.6.6
The RTCC can operate uninterrupted during Deep
Sleep mode. It can wake the device from Deep Sleep
by configuring an alarm.
The RTCC clock source is configured with the
RTCOSC bit (CONFIG3L<1>). The available reference
clock sources are the INTRC and T1OSC/T1CKI. If the
INTRC is used, the RTCC accuracy will directly depend
on the INTRC tolerance.For more information on
configuring the RTCC peripheral, see Section 16.0
“Real-Time Clock and Calendar (RTCC)”.
3.6.7
This section gives the typical sequence for using the Deep
Sleep mode. Optional steps are indicated, and additional
information is given in notes at the end of the procedure.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If using an RTCC alarm for wake-up, wait until
11. Enter Deep Sleep mode by setting the DSEN bit
12. Once a wake-up event occurs, the device will
13. Determine if the device exited Deep Sleep by
DS39931C-page 50
Enable DSWDT (optional).
Configure DSWDT clock source (optional).
Enable DSBOR (optional).
Enable RTCC (optional).
Configure the RTCC peripheral (optional).
Configure the ULPWU peripheral (optional).
Enable the INT0 Interrupt (optional).
Context save SRAM data by writing to the
DSGPR0 and DSGPR1 registers (optional).
Set the REGSLP bit (WDTCON<7>) and clear
the IDLEN bit (OSCCON<7>).
the RTCSYNC bit (RTCCFG<4>) is clear.
(DSCONH<7>) and issuing a SLEEP instruction.
These two instructions must be executed back
to back.
perform a POR Reset sequence. Code execution
resumes at the device’s Reset vector.
reading the Deep Sleep bit, DS (WDTCON<3>).
This bit will be set if there was an exit from Deep
Sleep mode.
DEEP SLEEP BROWN-OUT RESET
(DSBOR)
RTCC PERIPHERAL AND DEEP
SLEEP
TYPICAL DEEP SLEEP SEQUENCE
(3)
(1)
(1)
DD
supply rail
(3)
(2)
(4)
14. Clear the Deep Sleep bit, DS (WDTCON<3>).
15. Determine the wake-up source by reading the
16. Determine if a DSBOR event occurred during
17. Read the DSGPR0 and DSGPR1 context save
18. Clear the RELEASE bit (DSCONL<0>).
3.6.8
If during Deep Sleep, the device is subjected to
unusual operating conditions, such as an Electrostatic
Discharge (ESD) event, it is possible that internal cir-
cuit states used by the Deep Sleep module could
become corrupted. If this were to happen, the device
may exhibit unexpected behavior, such as a failure to
wake back up.
In order to prevent this type of scenario from occurring,
the
self-monitoring capability. During Deep Sleep, critical
internal nodes are continuously monitored in order to
detect possible Fault conditions (which would not
ordinarily occur). If a Fault condition is detected, the
circuitry will set the DSFLT status bit (DSWAKEL<7>)
and automatically wake the microcontroller from Deep
Sleep, causing a POR Reset.
During Deep Sleep, the Fault detection circuitry is
always enabled and does not require any specific
configuration prior to entering Deep Sleep.
Note 1: DSWDT
DSWAKEH and DSWAKEL registers.
Deep Sleep mode by reading the DSBOR bit
(DSCONL<1>).
registers (optional).
Deep
2: The DSWDT and RTCC clock sources
3: For more information, see Section 16.0
4: For more information on configuring this
DEEP SLEEP FAULT DETECTION
through the devices’ Configuration bits.
For more information, see Section 26.1
“Configuration Bits”.
are selected through the devices’ Con-
figuration bits. For more information, see
Section 26.1 “Configuration Bits”.
“Real-Time
(RTCC)”.
peripheral,
Low-Power Wake-up”.
Sleep
module
and
© 2009 Microchip Technology Inc.
see
Clock
DSBOR
Section 3.7
includes
and
are
Calendar
automatic
enabled
“Ultra